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fix(sim): keep clock copies sensed at the opposite edge apart - #1373
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A whole-variable copy of a clock joined its source's domain even when it was sensed at the opposite edge, so always_ff @(negedge c) with assign c = clk ran at clk's rising edge. Such a copy is now a clock derived from its source.
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A whole-variable copy of a clock joined its source's clock domain even when it was sensed at the opposite edge. With
assign c = clk;andalways_ff @(negedge c), the block ran on clk's rising edge. A Verylclock_negedgechild port connected to a rising-edge clock behaved the same way.unify_clock_domainsnow cuts a copy edge apart when its two ends are sensed at different edges, before it resolves canonical domains. A copy sensed at no edge takes the edge of its drivers, so chains such asassign c = clk; assign d = c; always_ff @(negedge d)are split, including chains through child ports. A root sensed at no edge, such as an SV input used only through copies, takes the edge of its first copy that is sensed at one. A copy that is cut off becomes a derived clock and fires on the source's falling edge, as IEEE 1800 requires.Sensing one signal at both edges is still rejected with an explicit error (#443).
Tests:
derived_register_clock.rsadds six cases: a Veryl internal copy, a Veryl falling-edge child port, SV@(negedge c), an SV chain of copies, an SV chain through a child port, and an unsensed SV input copied to both edges. All six fail on master.cargo nextest run --workspace --features celox/systemverilog: 13759 passed. clippy is clean.