Issues

• Evaluate and document Aplite sampling distribution guarantees

  celox-sim/celox#2187 · Filter by author tignear opened on Oct 26, 2026

• Outputs of one always @* / always_comb process feeding each other are reported as a combinational loop

  celox-sim/celox#2139 · Filter by author tignear opened on Oct 26, 2026

• SV two-state: case equality and case labels match X/Z literal bits as zero

  celox-sim/celox#2136 · Filter by author tignear opened on Oct 26, 2026

• SV: concurrent assertions (assert property) are a parse error (blocks rtlmeter E203)

  celox-sim/celox#2130 · Filter by author tignear opened on Oct 26, 2026
  1

• SV: accept loop temporaries shared by level-sensitive always blocks (blocks rtlmeter E203)

  celox-sim/celox#2129 · Filter by author tignear opened on Oct 26, 2026
  1

• SV: macros from one source file are not visible in later files of the same compilation (blocks rtlmeter VeeR-EL2/EH1)

  celox-sim/celox#2128 · Filter by author tignear opened on Oct 26, 2026
  2

• SV: non-ANSI port and net ranges are compared as text, rejecting equal ranges (blocks rtlmeter E902/E906)

  celox-sim/celox#2126 · Filter by author tignear opened on Oct 26, 2026
  1

• feat(sv): complete fork process control and persistence

  celox-sim/celox#2111 · Filter by author tignear opened on Oct 26, 2026

• Design: schedule the synthesizable part as reg' = ff(comb(reg)), one settle per clock edge

  celox-sim/celox#2103 · Filter by author tignear opened on Oct 26, 2026

• cranelift: wrong edges in a compiled scheduler with more than 64 events (128-bit masks)

  celox-sim/celox#2102 · Filter by author tignear opened on Oct 26, 2026

• sv: classes declared in loop generate blocks

  celox-sim/celox#2064 · Filter by author tignear opened on Oct 25, 2026

• perf(native): make the register allocator's whole-function analyses near-linear

  celox-sim/celox#2032 · Filter by author tignear opened on Oct 25, 2026
  2

• feat(cli): save state files at chosen cycles of a signal in celox run

  celox-sim/celox#2025 · Filter by author tignear opened on Oct 25, 2026

• perf: settle only the combinational partitions whose inputs changed

  celox-sim/celox#2013 · Filter by author tignear opened on Oct 25, 2026
  5

• perf(runtime): lift the 64-event limit of the compiled scheduler

  celox-sim/celox#2012 · Filter by author tignear opened on Oct 25, 2026

• perf: derived-edge units inline the combinational program twice per event

  celox-sim/celox#2011 · Filter by author tignear opened on Oct 25, 2026
  1

• SV symbolic lowering folds constants through literal strings

  celox-sim/celox#1993 · Filter by author tignear opened on Oct 25, 2026

• feat(vpi): run SV processes with celox-vpi-compile and celox-vpi-runtime

  celox-sim/celox#1983 · Filter by author tignear opened on Oct 25, 2026

• CodSpeed is failing on master

  celox-sim/celox#1975 · Filter by author github-actions opened on Oct 25, 2026
  1

• sv: assembly misses nonblocking package-variable writes of runtime processes

  celox-sim/celox#1969 · Filter by author tignear opened on Oct 25, 2026

• Edges of multi-bit event signals are judged on the low byte, not the LSB

  bug
  celox-sim/celox#1968 · Filter by author tignear opened on Oct 25, 2026
  1

• sv: four-state and string actuals of class parameters

  celox-sim/celox#1964 · Filter by author tignear opened on Oct 25, 2026

• sv: give struct and union types a declaration identity for class specializations

  celox-sim/celox#1963 · Filter by author tignear opened on Oct 25, 2026

• feat(sv): support non-ANSI port expressions

  celox-sim/celox#1953 · Filter by author tignear opened on Oct 25, 2026

• sv: module typedef of a class-scoped typedef that uses a module constant is rejected

  celox-sim/celox#1939 · Filter by author tignear opened on Oct 24, 2026