Memory Interfaces Handling

lib/ADL/base.rb

@@ -4,6 +4,10 @@
 module SimInfra
     # @@instructions -array of instruction description
     # shows result of our tests in interactive Ruby (IRB) or standalone
+    @@regfiles = [] unless defined?(@@regfiles)
+    @@interface_functions = [] unless defined?(@@interface_functions)
+    @@instructions = [] unless defined?(@@instructions)
+
     def self.serialize(msg= nil)
         require 'yaml'
         yaml_data = YAML.dump(
@@ -17,7 +21,7 @@ def self.serialize(msg= nil)
     end
 
     def self.state
-        yaml_data = YAML.dump(
+        YAML.dump(
             {
                 regfiles: @@regfiles.map(&:to_h),
                 interface_functions: @@interface_functions.map(&:to_h),

lib/ADL/builder.rb

@@ -29,7 +29,7 @@ def self.from_h(h)
 end
 
 # Basics
-module SimInfra  
+module SimInfra
     def assert(condition, msg = nil); raise msg if !condition; end
 
     @@instructions = []
@@ -53,9 +53,9 @@ def to_h
                 fields: @fields.map { |f| f.to_h },
                 frmt: @frmt,
                 asm_str: @asm_str,
+                feature: @feature,
                 code: @code.to_h,
                 map: @map.to_h,
-                feature: @feature,
             }
         end
 
@@ -75,15 +75,16 @@ def self.from_h(h)
     class InstructionInfoBuilder
         include SimInfra
 
-        def initialize(name, feature) 
-            @info = InstructionInfo.new(name, feature) 
-            @info.code = Scope.new(nil) 
+        def initialize(name, feature)
+            @info = InstructionInfo.new(name, feature)
+            @info.code = Scope.new(nil)
 
             @@interface_functions.each do |func|
+                next if func[:kind] == :memory
                 if !func[:return_types].empty?
                     @info.code.instance_eval "def #{func[:name]}(*args)
                         in_s = *args.map { |a| resolve_const(a) }
-                        in_stmt = [tmpvar(#{func[:return_types][0]})] 
+                        in_stmt = [tmpvar(#{func[:return_types][0]})]
                         in_stmt.concat(in_s)
                         return stmt :#{func[:name]}, in_stmt
                     end
@@ -101,10 +102,10 @@ def initialize(name, feature)
         end
 
         def encoding(frmt, fields, *args)
-            @info.fields = fields 
-            @info.frmt= frmt 
-            map args 
-            
+            @info.fields = fields
+            @info.frmt= frmt
+            map args
+
             sum_bits = 0
             for f in fields
                 sum_bits += Utility.get_type(f.value.type).bitsize
@@ -125,14 +126,19 @@ def Instruction(name, &block)
     class InterfaceBuilder
         include SimInfra
 
-        def Function(name, output_types = [], input_types = [])
-            @@interface_functions << {:name => name, :return_types => output_types, :argument_types => input_types}
+        def Function(name, return_types: [], argument_types: [], attrs: [], kind: nil)
+            @@interface_functions << {
+                name: name,
+                return_types: return_types,
+                argument_types: argument_types,
+                attrs: attrs,
+                kind: kind,
+            }
         end
     end
 
     def Interface(&blck)
         bldr = InterfaceBuilder.new()
-
         bldr.instance_eval &blck
     end
 
@@ -176,27 +182,27 @@ def self.from_h(h)
     end
 
     @@regfiles = []
-class RegisterFileBuilder
-  attr_reader :info
-
-  def initialize(name) 
-    @info = RegisterFileInfo.new(name)
-    @info.regs = []
-  end
-
-  def method_missing(name, *args)
-    if name.to_s.start_with?('r')
-      size = name.to_s[1..].to_i
-      instance_eval "def #{name}(sym, *args); @info.regs << Register.new(sym, #{size}, args.size > 0 ? args : []); end", __FILE__, __LINE__
-      @info.regs << Register.new(args[0], size, args.size > 1 ? args[1..] : [])
-    else
-      error "Unknown method #{name}"
+    class RegisterFileBuilder
+      attr_reader :info
+
+      def initialize(name)
+        @info = RegisterFileInfo.new(name)
+        @info.regs = []
+      end
+
+      def method_missing(name, *args)
+        if name.to_s.start_with?('r')
+          size = name.to_s[1..].to_i
+          instance_eval "def #{name}(sym, *args); @info.regs << Register.new(sym, #{size}, args.size > 0 ? args : []); end", __FILE__, __LINE__
+          @info.regs << Register.new(args[0], size, args.size > 1 ? args[1..] : [])
+        else
+          error "Unknown method #{name}"
+        end
+      end
+
+      def zero = :zero
+      def pc = :pc
     end
-  end
-
-  def zero = :zero
-  def pc = :pc
-end
 
     def RegisterFile(name, &block)
         bldr = RegisterFileBuilder.new(name)

lib/ADL/scope.rb

@@ -106,8 +106,27 @@ def zext(a, type) = stmt(:zext, [tmpvar(type), a])
     def get_reg(expr, regset, type) = rlet("_reg_#{next_counter}".to_sym, regset, type, expr)
 
     def write(rfile, reg, expr) = stmt(:write, [rfile, reg, expr])
-    def writeMem(addr, expr) = stmt(:writeMem, [addr, expr])
-    def readMem(addr, type) = stmt(:readMem, [tmpvar(type), addr])
+
+    def writeMem(addr, expr)
+      iface = @@interface_functions.find do |f|
+        f[:kind] == :memory &&
+          f[:name].to_s.start_with?('writeMem') &&
+          f[:argument_types] == [addr.type, expr.type]
+      end
+      raise "no memory interface declared for writeMem of #{expr.type}" unless iface
+      stmt(:writeMem, [addr, expr], iface[:name])
+    end
+
+    def readMem(addr, type)
+      iface = @@interface_functions.find do |f|
+        f[:kind] == :memory &&
+          f[:name].to_s.start_with?('readMem') &&
+          f[:return_types] == [type]
+      end
+      raise "no memory interface declared for readMem of #{type}" unless iface
+      v = tmpvar(type)
+      stmt(:readMem, [v, addr], iface[:name])
+    end
 
     def read(rfile, reg)
       v = tmpvar(:b32)

lib/Target/RISC-V/32I.rb

@@ -7,7 +7,13 @@ module RV32I
     extend SimInfra
 
     Interface {
-        Function(:sysCall)
+        Function(:sysCall, kind: :cpu)
+        Function(:readMem8,  return_types: [:b8],  argument_types: [:b32], kind: :memory)
+        Function(:readMem16, return_types: [:b16], argument_types: [:b32], kind: :memory)
+        Function(:readMem32, return_types: [:b32], argument_types: [:b32], kind: :memory)
+        Function(:writeMem8,  argument_types: [:b32, :b8],  kind: :memory)
+        Function(:writeMem16, argument_types: [:b32, :b16], kind: :memory)
+        Function(:writeMem32, argument_types: [:b32, :r32], kind: :memory)
     }
 
     RegisterFile(:XRegs) {

sim_gen/CPUState/cpu_state.rb

@@ -164,7 +164,7 @@ module SimGen
   module CPUState
     module Header
       module_function
-      
+
       def generate_cpu_state(input_ir)
         pc_decl = Helper.generate_pc_decl(input_ir[:regfiles])
         pc_functions = Helper.generate_pc_functions(input_ir[:regfiles])

sim_lib/Target/RISCV/cpu_state_ext.cc

@@ -1,4 +1,5 @@
 #include "cpu_state.hh"
+#include <cstdint>
 
 namespace prot::state {
 
@@ -13,4 +14,26 @@ void CPU::sysCall() {
   }
 }
 
+void CPU::writeMem8(uint32_t addr, uint8_t value) {
+  m_memory->write<uint8_t>(addr, value);
+}
+
+void CPU::writeMem16(uint32_t addr, uint16_t value) {
+  m_memory->write<uint16_t>(addr, value);
+}
+
+void CPU::writeMem32(uint32_t addr, uint32_t value) {
+  m_memory->write<uint32_t>(addr, value);
+}
+
+uint8_t CPU::readMem8(uint32_t addr) { return m_memory->read<uint8_t>(addr); }
+
+uint16_t CPU::readMem16(uint32_t addr) {
+  return m_memory->read<uint16_t>(addr);
+}
+
+uint32_t CPU::readMem32(uint32_t addr) {
+  return m_memory->read<uint32_t>(addr);
+}
+
 } // namespace prot::state