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Memory Interfaces Handling - #31

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uslsteen wants to merge 4 commits into
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* Memory interfaces registration was supported
* Minor formatting
* :writeMem, :readMem statements were preserved for
native simulator gen (backward compatibility)
* Memory Interfaces (function names) were set as statement attributes
* TODO:
    * move cpu_state.rb into common part of the sim gen scripting

    * Memory Access implementations were temporarily
      placed into arch specific sim library cpu_state_ext.cc
@uslsteen uslsteen self-assigned this Oct 27, 2026
@uslsteen uslsteen added help wanted Extra attention is needed ISA description Architecture Description Language related task RISC-V Issue or task related to RISC-V architecture enhancement New feature or request labels Oct 27, 2026
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enhancement New feature or request help wanted Extra attention is needed ISA description Architecture Description Language related task RISC-V Issue or task related to RISC-V architecture

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