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Replace design variable f with w to avoid Ansys intrinsic variable co… - #30

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sadda merged 3 commits into
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16-replace-f-with-w
Sep 8, 2026
Merged

sadda merged 3 commits into
mainfrom
16-replace-f-with-w

Move StopTime/TimeStep formula into the parent class using w

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pytest (3.12)
succeeded Sep 8, 2026 in 2m 19s