Silicon Design Engineer | VLSI Researcher | Open-Source EDA Contributor

I build and evaluate digital hardware across RTL, verification, physical implementation, timing, DFT and memory reliability. My research connects architectural choices to reproducible implementation evidence, including the experiments that reject an idea.

From architecture and RTL to verification, timing closure, and physical evidence.

GitHub · LinkedIn · Portfolio · ORCID 0009-0001-4892-5438

Projects · Upstream contributions · Experience · Activity

• Memory systems: SRAM protection, ECC hardware and conditional reliability–energy tradeoffs.
• RTL to implementation: digital architecture, independent verification, STA and routed evaluation.
• Design for test: scan architectures, ATPG, fault simulation and EDA automation.
• Computer architecture: programmable temporal I/O and bounded protocol operations.

Question: which protection hardware is preferable under a defined service, timing constraint and operation mix? GREENS connects ECC RTL and correctness checks to matched routed implementations and operation-energy evidence. Across four admitted SKY130 seed pairs, Hsiao used less ECC-logic energy in 4 of 20 seed/operation comparisons. The preference is workload dependent; no whole-SRAM energy winner is established.

Status: evidence-qualified research artifact; manuscript publication status is unverified. Tools: Verilog/SystemVerilog, Python, Yosys, OpenROAD/OpenSTA, SKY130HD and SRAM22 macros.

Code · Reproduce the claims · Claim-to-evidence index · Results and figure

Question: can placed geometry and ATPG switching guide scan orders whose gains survive routing? PACT searches legal orders and checks them through independent serial replay, routing and physical qualification. Nine frozen architectures qualified in the final static power-integrity study, but primary worst-drop improvements were only 3 µV and 8 µV: no material static IR-drop benefit under the registered conditions. Routed transfer was mixed.

Status: original hypothesis frozen; methodology and negative results retained. Tools: Python/C++, Tcl, OpenROAD, OpenSTA and FAN_ATPG. No transient-droop or thermal benefit is established.

Code · Reproduction and canonical results · Final physical report · Freeze decision

Question: can timestamped events decouple GPIO timing from producer latency? The M0 event engine reached GDS, STA/DRC/LVS and routed gate checks, with 48,000 randomized differential cycles and a 24-edge bounded formal check. Later guards and timestamps showed no baseline advantage; the final eventless SPI candidate failed autonomous CS framing.

Status: research closed; the verified M0 checkpoint is distinct from the unsuccessful later directions. Tools: SystemVerilog, Python, cocotb, Icarus, Verilator, Yosys and IHP CMOS5L. No fabricated-silicon result is claimed.

RTL and run instructions · M0 verification · M0 physical checkpoint · Final falsification

Question: how far can fixed-table compound operations generalize across serial protocols? Frozen v3 passed all 34 independently selected LIN break/sync-prefix cases, over 3,210,266 model/RTL cycles, without semantic changes. This is bounded prefix recognition, not full LIN compliance. Earlier reuse failures remain documented. One routed v3 attempt failed setup; the final attempt timed out.

Status: logical and matched-cost gates passed; physical qualification remains unestablished. Tools: SystemVerilog, Python, cocotb, Icarus, Yosys and IHP CMOS5L.

Code and verification · Runnable demonstrations · Architecture · Final campaign report

Inspect an actual RTL waveform: an interrupted LIN break produces no prefix token. Bounded digital simulation from MOTIF revision 9e4c500; unmodified Apache-2.0 asset, notice retained.

Implementation fixes, native regressions and minimal reproducers make the work inspectable beyond my own projects. These are contributions to other maintainers' repositories; my OpenSTA/OpenROAD repositories are contribution forks.

• 15 Oct 2026 · MERGED — OpenSTA #538. Reject unsupported wor/wand declarations before alias merging corrupts input connectivity. Issue #537 closed; wired-logic support is not implemented.
• 20 Oct 2026 · MERGED — OpenSTA #420. Preserve renamed input aliases; reject shared signal inputs before opening the output file; seven native regressions. Merged into The-OpenROAD-Project/OpenSTA.
• 21 Oct 2026 · MERGED — OpenSTA #540. Port the writer repair to canonical upstream with registered Tcl regressions. Original issue #536.
• 21 Oct 2026 · MERGED — OpenROAD #11624. Keep top ports on local module nets through child feedthroughs; add connectivity/DEF regressions. Merged into canonical upstream.

Open proposals, checked 24 Oct 2026: FAN_ATPG #4 repairs empty reports, scan identities and unsafe negative indexing. DFT #1 and DFT #2 target a maintainer's OpenROAD fork: compilation, fixed scan endpoints and metadata consistency. These are not upstream merges. FAN construction report #5 and fault identity report #6 preserve additional reproductions. Current automated status timeline.

• Cadence Design Systems — Product Validation / Quantus internship. Parasitic-extraction validation context.
• STMicroelectronics — Physical and Layout Design research internship. Physical/layout engineering context.
• M.Tech, ECE — VLSI and Embedded Systems, IIIT-Delhi, 2024–2026. GREENS originated at VICAS Lab under Dr. Anuj Grover.

Project evidence here is public research and open-source work; no proprietary implementation, customer data or company performance claims are included. Professional background · LinkedIn.

RTL: Verilog, SystemVerilog. Programming and automation: C++, Python, Tcl, Bash.
Verification: cocotb, Verilator, Icarus Verilog, differential simulation, bounded formal checks.
Physical implementation: Yosys, OpenROAD / ORFS, OpenSTA, STA; SKY130HD and IHP CMOS5L.
DFT: scan architectures, FAN_ATPG, fault simulation. Research: SRAM reliability, ECC and PPA tradeoffs.

Real GitHub data, refreshed approximately daily. The calendar shows API-visible contributions across eligible event types; the trend separates eligible commits, PRs, issues and submitted PR reviews. Counts can differ from GitHub's native calendar; exact parity is not asserted. Every graphic shows its coverage and publication dates. Anonymous restricted aggregates may appear if GitHub exposes them. Definitions and observed visibility limits · Selectable statistics, monthly values and timeline · Daily source data.

Open-source milestone graphic · Dark variant · Each milestone and its original evidence in text.

Model → implement → verify → evaluate physically → document what survives.