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Memory-level parallelism (MLP), phases 1 and 2 - #436

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tinebp wants to merge 126 commits into

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feature/mlp-phase2

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Memory-level parallelism (MLP), phases 1 and 2#436
tinebp wants to merge 126 commits into
masterfrom
feature/mlp-phase2

Commits on Oct 6, 2026
- simx: deliver same-cycle channel events in the order they were sent
  
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Commits on Oct 8, 2026
- sw, tests: make device index math portable to RV64
  
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Commits on Oct 10, 2026
- rtu: carry full-width scene and payload pointers on RV64
  
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  577a4af
- rtu: NaN-box single-precision slot reads into FP registers on RV64
  
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- gfx: store the depth plane modulo 2^32 instead of converting out of range
  
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- kernel: check vx_printf formats, and print vx_putint without a float detour
  
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  afd7acb
- sgemm_tcu_wg_dxa: widen the SW_LOAD_B index math, build SW_LOAD_A + SW_LOAD_B
  
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  2a8e29d
- tests: widen the index math of demo, fence, dogfood, softmax and sgemm_tcu
  
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  5d224d8
- Merge origin/master into rv64-fixes
  
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  5ad73c1
- rtu: carry the full scene address through the ray log and rt_replay
  
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  6c26b42
- config: hardware profiles shared by every flow
  
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Commits on Oct 11, 2026
- build: restore the zero-warnings policy everywhere
  
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  7b91e0e
- gen_config: accept enum flag overrides whose value contains '_'
  
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  57f28d2
- caps: report exact warp, core and cluster counts
  
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  4b924f2
- runtime: VORTEX_VM_MEGAPAGE_HEAP maps the heap with superpages
  
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  5f6d3e1
- simx: widen the cache config's input count and pipeline latency
  
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  4dbb615
- lsu: declare the LMEM window parameters only when LMEM exists
  
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  325d685
- tests: guard the global index in vecadd, relu, dropout and minimal
  
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  1642289
- cache: admit LLC fills against the AMO writeback queue's room
  
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  997ee24
- sim: redesign the DRAM model: independent channels, refresh, configurable type
  
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  843536c
Commits on Oct 12, 2026
- profiles: add a100, h100, v100, rtx1080 and tinygpu; document profiles
  
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  0897cbd
- CHANGELOG: profiles, RV64 portability, zero warnings, DRAM model
  
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  21861d6
- ci: default GEM5_HOME to the configured tool directory
  
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  49613f8
- ci: re-record the rtlsim perf-gate baselines
  
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  1c6ef7e
- tests: compute dogfood's fused multiply-add references fused
  
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  2970e9d
- vm: share one VPN superpage mask function from the TLB package
  
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  0a46eef
- sim: configure the DRAM model from data-sheet values
  
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  f80af4c
- simx: issue warps with the RTL's greedy round-robin arbiter
  
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  03efecb
- simx: let a cache bank pipeline hold one request per stage
  
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- ci: re-record the rtlsim perf-gate baselines for the DRAM model
  
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Commits on Oct 13, 2026
- Flush caches with one broadcast write and per-port flush tokens
  
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  046ff33
Commits on Oct 15, 2026
- Hash the cache bank select so power-of-two strides spread over the banks
  
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  ef75f8e
- Keep the other sectors' dirty bytes when a sector refills a line
  
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  bdf3953
- Let fills follow each other into a cache bank pipe back to back
  
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Commits on Oct 17, 2026
- Flush only the L1 caches between launches when the LLC is the coherence point
  
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Commits on Oct 18, 2026
- Let a write-back LLC allocate on a store miss without fetching the line
  
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  4f173e3
- core: decouple fetch width from issue width (VX_CFG_FETCH_WIDTH)
  
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  e587204
- simx: model the RTL's buffer structure at every pipeline boundary
  
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  285e946
- rtl: fix -DSCOPE builds of fetch, issue, LSU, TCU and graphics
  
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  397d7d2
- core: derive the core partitioning from the widths
  
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- simx: register the cache core-response port as the RTL does
  
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  e849c56
- simx: never launch two warps of one CTA into the same slot
  
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  6d7df03
- simx: model the depth of the cache networks
  
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  64c2039
- simx: register the icache core-response port as the RTL does
  
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  f367237
- ci: add a model_parity case for SGEMM on two frontend slices
  
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  6f3ea11
- Count global barriers across the whole device, not per cluster
  
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Commits on Oct 19, 2026
- Stop fences at the point of coherence and skip the walk for IO fences
  
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  3f27ba4
- Let a shared L3 answer L1-only flush tokens without a walk
  
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  9473f26
- Let the command processor's DMA use the shared last-level cache
  
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  1d3db49
- Check a victim's dirty bytes only when the victim way is valid
  
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  1de9126
- Serve a warp's identical loads with one dcache bank access
  
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  4e1d2a7
- Size the local-memory reservation hold budget by the core's harts
  
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  5e8e5c2
- Track MSHR misses in a line table so a cache can hold more in flight
  
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  75984cc
- tests: make mstress check every loaded value
  
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  227c49e
- simx: give each warp's instruction buffer its staging slot
  
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  f0b7504
- simx: send a fence to the data cache as a flush token
  
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  62dc764
- simx: stop fences at the point of coherence and skip the walk for IO fences
  
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  18b6fe5
- simx: serve a warp's identical loads with one dcache bank access
  
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  2342ffd
- simx: route a single cluster's global barrier through its arbiters
  
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- simx: track MSHR misses in a line table when MSHR_LINES is set
  
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  46080c0
- simx: let each slice of a cache arbiter tree grant on its own
  
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  a2b16ad
- simx: register a shared cache's input arbiter as the RTL does
  
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- simx: let the command processor's DMA use the shared last-level cache
  
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  bbad636
Commits on Oct 20, 2026
- Build VX_csr_fpu only when the F extension is enabled
  
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  fd151ef
- rtlsim: ask the processor whether the CP DMA is an LLC client
  
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  cc7bb17
- simx: drop the extra register on the LSU's path to commit
  
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  5475438
- dxa: stream GMEM responses straight to smem_wr again
  
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  14f944c
- Include VX_define.vh before VX_csr_fpu's F-extension guard
  
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  9e95002
- hw/unittest: test the CP DMA port's launch fence
  
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  360cd99
- docs: select the FPGA target with blackbox.sh --target
  
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  64f4268
- Round-robin the DXA and TCU on the LMEM DMA port
  
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Commits on Oct 21, 2026
- Size each slice of a stream arbiter tree by its own requests
  
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- simx: let a cache's port arbiter take more than 64 ports
  
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- Keep each uncached request on its own memory port when a cache has fewer core ports
  
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- lsu: select the stack-interleave high bits instead of adding the correction
  
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  18cccfd
- core: decide the warp-control unit's ready from the opcode
  
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  5a3e84f
- simx: hold off a local-memory read after any write and release the coalescer input early
  
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  f0667eb
- simx: launch each cluster on the nearest ready core
  
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  b3cad81
- simx: count a core's cycles only while it has work
  
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  4470f27
- ci: size the fp16-mc parity case like its perf_gate twin
  
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  7039eea
- CHANGELOG: memory-level parallelism, phase 1
  
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- tests: render raycast at 64x64 by default
  
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Commits on Oct 22, 2026
- cache: size the flush-token attribute and hash input to their fields
  
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  4faf32c
- simx: let the CP LLC port build in the functional simulator
  
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- core: give each LSU block its own memory path
  
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- core: export the LSU blocks' status bits instead of combining them in the core
  
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  304e0db
- core: keep each SFU block's CTA context RAM in the block
  
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  8410590
- tcu: give each TCU block its own metadata port into its slice's LSU scheduler
  
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- tcu: move the TCU_LD AGU into each TCU block and drop its gather buffer
  
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Commits on Oct 23, 2026
- core: drop the live-warps CSR bits above XLEN explicitly
  
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  365895a
- core: support a warp count per issue slice that is not a power of two
  
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  e311957
- hw/unittest: wire the tcu and tensor wrappers to the per-block TCU memory port
  
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  0c603f4
- afu: let the memory ports keep many transactions in flight
  
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Commits on Oct 24, 2026
- cache: route a crossbar input's ready from its own output, drain slices before a token
  
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  f93df32
- profiles: per-partition fetch and the CP as an LLC client on the GPU shapes
  
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  c5ed76a
- Support core, socket and cluster counts that are not powers of two
  
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  1a3055f
- ci: re-record perf baselines for the MLP Phase 1 timing
  
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  2183b6a
- afu: one AXI port per GPU memory port, W forwarded with its AW
  
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  afd4331
Commits on Oct 26, 2026
- simx: model the miss path's buffers and registered stages
  
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  78f2d2c
- cache: refetch a fully written lazy-fetch sector without a memory read
  
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  05d1237
- simx: model KMU, CTA retirement, barrier and collector timing
  
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  73db36c
- runtime: stage kernel args in clean slots without a cache flush
  
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  347c914
- simx: feed full-bandwidth ALU and FPU straight from the dispatch queue
  
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  3981976
- lsu: split memory fences into acquire and release, order .aq/.rl AMOs
  
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  03e8304
- core: keep the dcache tag whole on passthru lanes so port 0 reads merge
  
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  d6be497
- cache: drop .aq/.rl fences at a coherent dcache, add a bank-0 delay knob
  
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  a010af4
- ci: require a debug build to match release cycles (release_parity)
  
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  b9e7a24
- tcu: fp32-only output, bit-exact TFR numerics in SimX, tcu_unit test
  
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  009a9d5
- ci: check fence_mp's release fence and .rl atomic behind a slow bank 0
  
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  8206c72
- cache: merge same-line icache fetches from a core's fetch slices
  
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  c9b7816
- cache: keep a draining write-through chain pending, retime bank paths
  
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  1babe84
- simx: match LSU ingress, SFU result buffers and lmem crossbar to RTL
  
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  32432bb
- cache: fix a lazy-fetch dcache deadlock between AMO write-back and fills
  
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  d0cb49c
- syn: read vortex_afu.v as SystemVerilog in the Vivado flows
  
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  5391be5
- simx: keep the last-level cache across a launch reset
  
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  7820027
- ci: re-record the perf_gate baselines for the MLP changes
  
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  b671705
- docs: add the memory-level parallelism design document
  
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  c08c245
- syn: leave the XRT platform top out of the yosys AFU DUT
  
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  2339de0
- Merge origin/master into feature/mlp-phase2
  
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  058d0e7
- ci: split the model_parity and perf_gate cells into hour-long shards
  
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  1578b79
- simx: keep a straddling instruction's low half until decode takes it
  
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  3500f0a
- core: drop the MUFU instance the master merge left in VX_sfu_unit
  
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  29c250d
- ci: re-record the perf_gate baselines after the master merge
  
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  48f4e42
- core: read the RTU perf counters through the MPM DCR window
  
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Commits on Oct 27, 2026
- AGENTS: drop the proposals section
  
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- afu: pass the AXI memory ports to VX_afu_wrap as flat buses
  
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  3f25c83

Commits

Commits on Oct 6, 2026

Commits on Oct 8, 2026

Commits on Oct 10, 2026

Commits on Oct 11, 2026

Commits on Oct 12, 2026

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Commits on Oct 15, 2026

Commits on Oct 17, 2026

Commits on Oct 18, 2026

Commits on Oct 19, 2026

Commits on Oct 20, 2026

Commits on Oct 21, 2026

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Commits on Oct 23, 2026

Commits on Oct 24, 2026

Commits on Oct 26, 2026

Commits on Oct 27, 2026