Skip to content

simx: reject LMEM configurations that are rejected in RTL #433

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
eyoon1131 wants to merge 1 commit into
base: master
Choose a base branch
from
Open

simx: reject LMEM configurations that are rejected in RTL #433

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
9 changes: 9 additions & 0 deletions sim/simx/core.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -124,6 +124,15 @@ class Core::Impl {
mem_coalescers_.at(b) = MemCoalescer::Create(sname, LSU_CHANNELS, DCACHE_CHANNELS, DCACHE_WORD_SIZE, LSU_QUEUE_OUT_SIZE, 1);
}

#ifdef VX_CFG_TCU_WGMMA_ENABLE
static_assert(VX_CFG_LMEM_ENABLED, "TCU_WGMMA_ENABLE requires LMEM_ENABLE");
static_assert(VX_CFG_LMEM_LOG_SIZE <= 16, "LMEM exceeds the 16-bit smem descriptor offset field");
#endif
#ifdef VX_CFG_LMEM_ENABLE
static_assert(0 == ((uint64_t(1) << VX_CFG_LMEM_LOG_SIZE) % VX_CFG_MEM_BLOCK_SIZE), "LMEM size must be a multiple of MEM_BLOCK_SIZE");
static_assert(0 == (uint64_t(VX_MEM_LMEM_BASE_ADDR) % (uint64_t(1) << VX_CFG_LMEM_LOG_SIZE)), "LMEM base address must be aligned to the LMEM size");
#endif

// create local memory.
// The DXA writes and the TCU tile-buffer reads share the row-wide DMA
// port, DXA first.
Expand Down
Loading