#
xcelium
Here are 14 public repositories matching this topic...
Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
simulation verilog vcs synthesis vivado systemverilog fixed-point floating-point icarus-verilog iverilog icarus verilator xrun synthesizable xcelium irun ncsim
-
Updated
Jan 13, 2021 - SystemVerilog
UVM-Based Verification Project for a YAPP (Yet Another Packet Protocol) Router
-
Updated
Mar 28, 2025 - SystemVerilog
Simulator-agnostic transaction recording, visualization, and regression diffing for SystemVerilog/UVM verification. One DPI layer runs on Verilator, VCS, and Xcelium. See everything. Prove anything.
waveform verification eda vcs regression-testing systemverilog uvm verilator xcelium chip-design transaction-debugging
-
Updated
Sep 18, 2026 - Python
This project implements a digital clock with alarm functionality in Verilog and SystemVerilog.
-
Updated
Jun 26, 2023 - SystemVerilog
Specification-driven SystemVerilog/UVM verification of a 32-bit RISC-V Bit Manipulation Unit, with assertions, coverage, and reproducible bug evidence.
verification riscv regression-testing systemverilog uvm testbench sva hardware-verification xcelium functional-coverage
-
Updated
Sep 23, 2026 - SystemVerilog
Mixed-language UVM + VHDL networking cluster — dual-clock buffer, end-to-end scoreboard, live config
-
Updated
Aug 26, 2026 - SystemVerilog
grep for waveforms — read signal values, clock frequency, and transitions from Synopsys FSDB, Cadence SST2, and open VCD dumps, straight from the shell. Deterministic output, runs locally, no viewer. CLI + MCP server + Claude Code skill.
cli mcp waveform eda verilog systemverilog gtkwave uvm vcd verdi ai-agents fsdb design-verification xcelium simvision sst2 llm rtl-simulation claude-code claude-code-skill
-
Updated
Sep 8, 2026 - Python
Códigos das atividades e trabalhos das Disciplinas Sistemas Eletrônicos Digitais Reconfiguráveis e Projeto Integrador 3 (SEDR + Circuitos Integrados)
-
Updated
Sep 10, 2026 - Verilog
Specman/e UVC for a credit-based multi-flow arbiter — independent checker, constrained traffic, Xcelium integration
-
Updated
Aug 26, 2026 - E
Configurable AXI arbiter (Round Robin / Fixed Priority + Aging) — RTL verified in Vivado, implemented on Xilinx Artix-7, UVM testbench verified on Xcelium 25.03
fpga verification vivado systemverilog uvm axi xcelium hardware-design rtl-design-and-verification rtl-design-and-simulation
-
Updated
Sep 22, 2026 - SystemVerilog
UVM verification of a programmable egress QoS scheduler — SP/WRR arbitration, reference model, SVA, coverage
-
Updated
Aug 26, 2026 - SystemVerilog
Add this topic to your repo
To associate your repository with the xcelium topic, visit your repo's landing page and select "manage topics."