cpu-simulation

A survey on architectural simulators focused on CPU caches.

Tera - A simulated ternary (base 3) CPU, assembly language, assembler and decompiler. Uses trytes made up of 9 trits rather than bytes of 8 bits.

These are various files pertaining to a CPU I designed. Can be used in conjunction with my Logisim CPU youtube video series.

Simple TLB (Translation lookaside buffer) implementation on verilog.

This is an implementation of a simple CPU in Logisim and Verilog.

Simple RISC-V CPUs running a baremental ray-tracer program.

CPU Cache Simulation using gem5

CENOS: The Modern CPU Simulator

16-Bit RISC Based CPU Design and Simulation in Python

designing a 8-bit CPU for fun

Logic gate & circuit simulation framework; 8-bit CPU simulation.

Cycle-accurate simulator of a RISC-V core

The project will simulate a simple computer system consisting of a CPU and Memory.

6502 CPU simulator

Simply the simulated version of the CPU based on 'Reptile' design. It takes an assembly code file as input and shows the final state of all registers and data memory.

A binary port of Tera

Intel8085-Simulator: An ongoing project to create a simulator for the Intel 8085 microprocessor. Users can run binary files containing Intel 8085 opcodes and observe their execution. Feel free to use this brief description as needed! 🚀

An Assembly Language Parser and Evaluator written in Haskell using Parsec. Parses and executes assembly-like code, simulating a CPU with registers, flags, stack, and control flow instructions.

Sistema operativo distribuido en Go, simula los componentes principales de un SO moderno. Implementa un kernel con planificadores de procesos (FIFO, SJF, SRT), módulo de CPU con TLB y cache, gestión de memoria virtual con paginación multinivel y SWAP, y dispositivos I/O. Estos se comunican mediante APIs HTTP ejecución distribuida en múltiples VMs.

Simulated a custom 3-stage pipelined processor in Java from a formal spec: Harvard architecture with separate instruction/data memory, a 12-instruction custom ISA, 64 registers, a status register with 5 condition flags, and pipelined fetch-decode-execute with cycle-accurate timing.