Skip to content
#

compliance-testing

Here are 23 public repositories matching this topic...

Fault-tolerant RV32E RISC-V core in SystemVerilog. Features TMR PC/ALUs, DMR fail-safe control unit, and SEC-DED ECC regfile. Complete RTL-to-GDSII ASIC implementation in Cadence Genus & Innovus on 90nm standard cells @ 100 MHz (0.0 ps slack, 0 DRC/LVS violations, GDSII layout verified).

  • Updated Oct 14, 2026
  • Verilog

Fictional digital-asset custody mock built to be tested: a four-layer Playwright + TypeScript architecture (Zod contract oracle, deterministic workflows, thin UI, required compliance gate), a planted-defects demo branch the suite catches red-handed, a self-auditing agent panel, and a perf layer proving contention correctness on SQLite.

  • Updated Jul 20, 2026
  • TypeScript

Add this topic to your repo

To associate your repository with the compliance-testing topic, visit your repo's landing page and select "manage topics."

Learn more