gm/Id design toolkit: lookup tables, design charts, and automated multicorner sizing of analog circuits
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Updated
Sep 22, 2026 - Python
gm/Id design toolkit: lookup tables, design charts, and automated multicorner sizing of analog circuits
Quantum circuit optimizer developed by ICEPP and LBNL
ZX-Calculus graph rewrite engine applying spider fusion, phase addition modulo 2pi, and identity reduction to optimize quantum circuit T-count.
ZX-Calculus graph rewrite engine applying spider fusion, phase addition modulo 2pi, and identity reduction to optimize quantum circuit T-count.
A transpiler pass for Qiskit which uses ZX-Calculus for circuit optimization, implemented using PyZX.
Hardware-tailored readout/preparation circuit optimization on small quantum systems.
The verified quantum circuit optimizer. Smaller circuits, proven.
ATLAS: topology-aware Bayesian optimization for analog transistor sizing using Mapper/TDA, ngspice, GF180MCU, and SKY130 (ICCAD 2026).
Cadence Virtuoso plugin for AmpSys analog sizing optimization with Windows LUT build and Linux cache-only flow.
Structural diagnostic tool for multi-chip quantum systems. Built by a carpenter. Benchmarks are honest about what is simulation and what is hardware. Patent pending. pip install rozier-quantum
Decrypt QQ Music files with C-accelerated performance, metadata, and lyrics support.
Verified 29-AND AES forward S-box circuit with reproducible SLP/XAG/net artifact
Verified 29-AND AES forward S-box circuit with reproducible SLP/XAG/net artifact
Verified 29-AND AES forward S-box circuit with reproducible SLP/XAG/net artifact
Verified 29-AND AES forward S-box circuit with reproducible SLP/XAG/net artifact
Verified 29-AND AES forward S-box circuit with reproducible SLP/XAG/net artifact
Verified 29-AND AES forward S-box circuit with reproducible SLP/XAG/net artifact
Verified 29-AND AES forward S-box circuit with reproducible SLP/XAG/net artifact
rqm-optimize compresses single-qubit gate runs into shorter SU(2)-equivalent forms, reducing unnecessary depth without changing the user workflow.
Verified 29-AND AES forward S-box circuit with reproducible SLP/XAG/net artifact
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