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Neural Network in Verilog - Work in Progress

academic-project fpga machine-learning neural-network verilog

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Name		Name	Last commit message	Last commit date
.gitignore		.gitignore
Adder.sv		Adder.sv
ArchCtrl.sv		ArchCtrl.sv
Architecture.sv		Architecture.sv
Control.sv		Control.sv
LICENSE		LICENSE
Multiplier.sv		Multiplier.sv
Network.sv		Network.sv
Neuron.sv		Neuron.sv
Neuron_ReLU.sv		Neuron_ReLU.sv
Neuron_Sigmoid.sv		Neuron_Sigmoid.sv
Pattern.sv		Pattern.sv
README.md		README.md
ReLU.sv		ReLU.sv
Sigmoid.sv		Sigmoid.sv
archtest.sv		archtest.sv
control_test.sv		control_test.sv
mat.sv		mat.sv
new.sv		new.sv
one.sv		one.sv
pattern_test.sv		pattern_test.sv
test.sv		test.sv
topmodule.sv		topmodule.sv
toptest.sv		toptest.sv

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NeuralNet

About

Neural Network in Verilog - Work in Progress

academic-project fpga machine-learning neural-network verilog

2 stars

1 watching

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