[lins-code54]

Summary

Adds Cadence as a third EDA target on the Export page, next to Altium and KiCad. Like those targets it writes library files that the user imports; SeEx itself runs no Cadence program.

Output	What it is	How it gets into Cadence
<lib>.xml	OrCAD Capture Library XML with every symbol	Capture: File > Import > Library XML → .olb
<lib>_allegro/*.il	one Allegro SKILL script per footprint, plus <lib>.il	Allegro PCB Editor command window: skill load("<lib>_allegro/<lib>.il") builds .dra, .psm and .pad in that folder
<lib>_step/*.step	3D models	mapped on each footprint where EasyEDA places them; add the folder to STEPPATH

Capture's .olb and Allegro's .dra / .psm / .pad are undocumented binary formats that only Cadence writes, so these are the formats Cadence reads in their place. Ultra Librarian and SamacSys deliver Capture symbols the same way.

Footprints

• Standard SMD packages (chip R/C/L/LED/diodes, SOT, SOD, DO-214, SOIC/SOP, QFP, QFN/SON) get IPC-7352 land patterns at density level N, named by the IPC convention (RESC1005X40N, SOT95P280X145-5N, …). Each pattern is checked against the manufacturer's lands, and EasyEDA's pin numbers are carried over.
• Other packages keep the manufacturer's lands, with IPC-7352 courtyard, silkscreen and place-bound rules.
• Silkscreen is 0.12 mm, clipped 0.2 mm from copper, with a polarity mark. The reference designator is sized to the part on the silkscreen and centred on the assembly layer.

3D logo removal (all targets)

• The EasyEDA logo (watermark) is now removed from downloaded 3D models by default, for Altium, KiCad and Cadence. The logo is cut out and the model is rebuilt. The rebuilt model is only used if every shell is still closed and no reference is left dangling.
• If the logo cannot be removed safely, the original model is exported and the part is listed in the export result: Models with logo: …, also shown in red under the run panel.
• The new Remove 3D logo toggle turns removal off.
• The existing kicad::step_sanitizer is not used by any export path, so it is left untouched.

Other

• Append, Force, Continue on error and English metadata behave as they do for KiCad. Without Append, an existing Cadence library is refused, as the KiCad and Altium targets do.
• STEP downloads fall back to modules.easyeda.com when modules.lceda.cn cannot be reached (seen as a TLS handshake failure on some networks).
• No 3D preview is added, in line with the README.

Testing

• cargo clippy --locked --all-targets --all-features -- -D clippy::correctness -D clippy::suspicious passes.
• cargo test --locked passes: 215 tests (Windows).
• rustfmt --edition 2024 --check is clean.
• Exported 10 real parts (C25744, C1525, C14663, C2286, C466657, C20917, C6186, C2040, C165948, C2826547) and checked them with Cadence SPB 26.1:
  • Capture's own XML import produced an .olb with all 10 parts and their PCB footprints.
  • Running the library script in Allegro built all 10 .dra/.psm files and their padstacks.
  • The STEP models sit on their pads.
  • All 10 models came out without the logo.