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rajinthanr/README.md

Rajinthan Rameshkumar

Electronic & Telecommunication Engineering · University of Moratuwa '27

Analog & mixed-signal ICs · Embedded systems · FPGA design · Robotics

Portfolio CV LinkedIn Email

GPA Microelectronics Olympiad Location

About me

I build and test hardware across silicon, firmware, and control systems. At NUS StarLabs, I worked on a 100 mNms smart reaction wheel controller for satellite attitude control, including field-oriented control and BLDC motor sensing. At RoboticGen, I developed STM32-based robotics hardware, including a motor-control PCB that reduced board size by 40% and a 4WD platform that reached 3 m/s.

Selected work

Project What I built Evidence
Two-stage CMOS op-amp SKY130 design for Tiny Tapeout; 80 dB gain, 4 MHz unity-gain bandwidth, 2 nA disable current Repository
2.4 GHz fractional-N PLL and LC-VCO Open-source IHP SG13G2 team design; associated with an accepted SMACD 2026 paper Repository · Preprint
Open-source micromouse STM32F405 control PCB, encoder feedback, PID tuning and maze navigation; RoboticGen's OBO Mouse v4 Repository · Development build
4-way set-associative cache Write-back Verilog cache with non-blocking MSHR support, 1 KB as built and parameterised to 64 KB; verified in simulation, synthesised for DE0-Nano Repository
NFC attendance logger STM32L432 + ST25R3916 board and low-power firmware that logs card taps and mounts as a USB drive, with a PySide6 companion app Repository

Current research: Low-power noise-shaping SAR ADC in SKY130 CMOS for energy-constrained sensing applications.

Experience & recognition

  • Research Intern · NUS StarLabs (Dec 2025–Jun 2026): smart reaction wheel controller for satellite ADCS; FOC algorithms and Alva BLDC motor sensing.
  • Robotics Team Member · RoboticGen (Apr 2025–Jan 2026): 4WD robotics, STM32F405 motor-control hardware, PID control and sensor integration.
  • 3rd globally at the 20th International Microelectronics Olympiad; Champion of IEEE Chips Challenge 2025.

Tools & technologies

Programming & systems
C C++ Python Verilog MATLAB Linux

IC design & EDA
Cadence xschem ngspice KLayout SKY130A IHP SG13G2

Embedded, FPGA & hardware
STM32 ESP32 Quartus ModelSim Altium KiCad

Research interests: analog and mixed-signal ICs · RF and high-frequency ICs · power-efficient SoCs · IC layout optimization · FPGA-based prototyping · edge computing for IoT devices

📍 Colombo, Sri Lanka · Let's connect

Pinned Loading

  1. ttsky_opamp ttsky_opamp Public

    Two-stage CMOS op-amp in SKY130 for Tiny Tapeout: schematic, layout and post-layout simulation

    Tcl 1

  2. end-effector end-effector Public

    Reconfigurable vacuum-and-fork end effector for robotic depalletizing: SolidWorks, PCB and ATmega2560 firmware

    HTML 1

  3. rgen-micromouse rgen-micromouse Public

    Open-source micromouse: STM32F405 firmware (flood fill, diagonal runs), custom PCB and 3D-printed drive

    C++ 1

  4. common-source-amplifier common-source-amplifier Public

    Common-source amplifier in SKY130A designed with IIC-OSIC-TOOLS: xschem, ngspice and layout

  5. digital-system-design digital-system-design Public

    Quartus FPGA exercises in Verilog and block diagrams: adders and a sequence detector

    Verilog

  6. set-associative-cache set-associative-cache Public

    4-way set-associative write-back cache in Verilog with LFSR replacement and MSHR-based non-blocking misses

    Verilog