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Prepare qcom-next based on tag 'Linux 7.4-rc1' of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git - #1414
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Add support for the Qualcomm Shikra SoC to the protection domain mapper. All Shikra SoC variants (CQM, CQS, IQS) share the same protection domain requirements: cdsp_root_pd, mpss_root_pd, mpss_wlan_pd. Signed-off-by: Anurag Pateriya <anurag.pateriya@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20261030-shikra_pd-v2-1-09bd0394629b@oss.qualcomm.com
Whenever virtual channel slot allocation changes, the DP source must send the action control trigger sequence to notify the sink about the same. This would be applicable during the start and stop of the pixel stream. Add the infrastructure to be able to send ACT packets for the DP controller when operating in MST mode. Add REG_DP_MST_ACT, the ACT trigger register used by this sequence. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260831-msm-dp-mst-v6-8-c91d35d6fb9e@oss.qualcomm.com/
Add support to program the MST enable bit in the mainlink control register when an MST session is active or being disabled. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260831-msm-dp-mst-v6-9-c91d35d6fb9e@oss.qualcomm.com/
DP stream is transmitted in transfer units only for SST case, there is no need to calculate and program TU parameters for MST case. Skip the TU programming for MST cases. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260831-msm-dp-mst-v6-10-c91d35d6fb9e@oss.qualcomm.com/
…se cases As per the hardware programming guide, MST_FIFO_CONSTANT_FILL must always be programmed when operating in MST mode. Ensure the register is configured accordingly. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260831-msm-dp-mst-v6-11-c91d35d6fb9e@oss.qualcomm.com/
…roller The VC Payload Fill (VCPF) sequence is inserted by the DP controller when stream symbols are absent, typically before a stream is disabled. Add support for triggering the VCPF sequence in the MSM DP controller. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260831-msm-dp-mst-v6-12-c91d35d6fb9e@oss.qualcomm.com/
DP MST streams share 64 MTP slots in a time-multiplexed manner. Add support for calculating the rate governor, slot allocation, and slot reservation in the DP controller. Each MST stream can reserve its slots by calling msm_dp_display_set_stream_info() from its bridge callbacks. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260831-msm-dp-mst-v6-13-c91d35d6fb9e@oss.qualcomm.com/
The power_on boolean cannot represent DP MST, where multiple streams share a single link and its associated resources. Replace power_on with active_stream_cnt and use it to track the lifetime of the shared link. Link initialization is performed when enabling the first stream, while link teardown is deferred until the last stream is disabled. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260831-msm-dp-mst-v6-14-c91d35d6fb9e@oss.qualcomm.com/
…ting a panel The atomic bridge callbacks (set_mode / enable / disable / post_disable) on dp_display currently hard-code dp->panel. For DP MST every stream has its own msm_dp_panel that the MST encoder owns, so the same enable/disable sequence needs to be invokable against an arbitrary panel. Introduce *_helper variants that take struct msm_dp_panel * and reduce the existing atomic_* callbacks to thin wrappers that pass dp->panel. No SST-path behaviour change. Also drop the static qualifier from msm_dp_display_prepare_link() and msm_dp_display_unprepare() and change them to take struct msm_dp * so the upcoming MST encoder code can drive link-level prepare/unprepare uniformly through the public API. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260831-msm-dp-mst-v6-15-c91d35d6fb9e@oss.qualcomm.com/
In MST mode, multiple streams share the same DP link. Track a link_ready state so msm_dp_display_prepare_link() runs only once per link and repeated calls are skipped. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260831-msm-dp-mst-v6-16-c91d35d6fb9e@oss.qualcomm.com/
… panel Add an API msm_dp_display_get_panel() to initialize and return a DP panel to be used by DP MST module. Since some of the fields of DP panel are private, dp_display module needs to initialize these parts and return the panel back. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260831-msm-dp-mst-v6-17-c91d35d6fb9e@oss.qualcomm.com/
Add a dedicated schema for the PCIe controller found on the Shikra platform. Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260701-shikra-upstream-v1-2-e1a721eb8943@oss.qualcomm.com
Add the dp_mst_drm module and the core MST manager data structures. Introduce the MST manager object, per-stream encoder state and the initialization path for creating a DRM MST topology manager associated with a DP controller. Also add the registration hooks used to initialize the MST manager during DP device setup. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260831-msm-dp-mst-v6-18-c91d35d6fb9e@oss.qualcomm.com/
Register the add_connector topology callback with the DRM MST manager to create DRM connectors dynamically for MST ports as they appear. Each MST port is represented by a DRM connector. The connectors are attached to all available MST stream encoders, allowing encoder assignment to be determined dynamically rather than being permanently associated with a specific stream. This enables MST sink ports to be exposed as DRM connectors. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260831-msm-dp-mst-v6-19-c91d35d6fb9e@oss.qualcomm.com/
Derive the controller ID from disp_info->h_tile_instance[index] instead of passing it separately to dpu_encoder_get_intf(). This removes a redundant argument and keeps all interface selection parameters in msm_display_info. No functional change. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260831-msm-dp-mst-v6-20-c91d35d6fb9e@oss.qualcomm.com/
Add devicetree bindings for TC9563 GPIO's which are used to control endpoint power and reset. Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260701-shikra-upstream-v1-3-e1a721eb8943@oss.qualcomm.com
For MST, multiple streams can share the same DP controller, making (controller_id, intf_type) insufficient to uniquely identify a DPU interface. Add stream_id to msm_display_info and use it to select the matching interface for a stream. For DSI, eDP and SST configurations, stream_id remains zero and behavior is unchanged. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260831-msm-dp-mst-v6-21-c91d35d6fb9e@oss.qualcomm.com/
Add support for the single PCIe controller on Shikra platform which is capable of Gen2x1 operation. Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260701-shikra-upstream-v1-4-e1a721eb8943@oss.qualcomm.com
Unlike SST, where a DP controller is represented by a single encoder, MST requires an encoder instance for each stream. Create one DRM encoder per MST stream, associate it with a stream ID, and initialize it with MST-specific encoder helper callbacks. This establishes the per-stream encoder infrastructure required for DP MST support. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260831-msm-dp-mst-v6-22-c91d35d6fb9e@oss.qualcomm.com/
Shikra supports single PCIe instance with 5GT/s x1 lane. Add PCIe controller and PHY node for this single instance. Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260701-shikra-upstream-v1-7-e1a721eb8943@oss.qualcomm.com
Add the atomic check, enable and disable operations for MST streams. Reserve VC payload bandwidth based on the negotiated link parameters, and update the MST payload when enabling or disabling each DP stream. Serialize stream updates that access the shared MST link state. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260831-msm-dp-mst-v6-23-c91d35d6fb9e@oss.qualcomm.com/
Add HPD callback for the MST module which shall be invoked from the dp_display's HPD handler to perform MST specific operations in case of HPD. In MST case, route the HPD messages to MST module. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260831-msm-dp-mst-v6-24-c91d35d6fb9e@oss.qualcomm.com/
…aths Call drm_dp_mst_atomic_check() from msm_atomic_check() so MST-specific state, such as connector and topology changes, is validated as part of the atomic check. Hook the MST helpers into atomic_commit_setup() and atomic_commit_tail() to support non-blocking atomic commits for DisplayPort MST, and ensure MST commits properly wait for dependencies. For SST, non-blocking commits are already handled via commit_tail(), which waits for dependencies in the DRM core. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260831-msm-dp-mst-v6-25-c91d35d6fb9e@oss.qualcomm.com/
…tive The bridge detect function is only applicable for SST. In MST mode, connector detection is handled by MST bridges. Skip detection for the SST bridge when MST is active, matching the behavior of other DP MST implementations. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260831-msm-dp-mst-v6-26-c91d35d6fb9e@oss.qualcomm.com/
…or PCIe Add a node for the TC9563 PCIe switch connected to PCIe. The switch has three downstream ports.Two embedded Ethernet devices are present on one of the downstream ports. All the ports present in the node represent the downstream ports and embedded endpoints. Power to the TC9563 is supplied through two LDO regulators, which are on by default and are added as fixed regulators. TC9563 can be configured through I2C. Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260701-shikra-upstream-v1-8-e1a721eb8943@oss.qualcomm.com
… node Enable the PCIe PHY for the single PCIe intance on the Shikra CQS, CQM and the IQS platforms. IQS platform uses a different powergrid than CQS/CQM which explain the different PHY supplies for IQS variant. Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260701-shikra-upstream-v1-9-e1a721eb8943@oss.qualcomm.com
…ompatible On platforms where the modem DMAs into the BAM-DMUX RX data buffers and the XPU enforces per-region access control, each individually DMA-mapped RX buffer consumes an XPU resource group. With only ~16 groups available, the per-buffer mappings exhaust the table and inbound transfers fault. Add qcom,shikra-bam-dmux as an additional compatible for the Shikra SoC, paired with the generic qcom,bam-dmux fallback, so the driver can match on it via its of_device_id table. Co-developed-by: Deepak Kumar Singh <deepak.singh@oss.qualcomm.com> Signed-off-by: Deepak Kumar Singh <deepak.singh@oss.qualcomm.com> Signed-off-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260714-qcom-bam-dmux-vmid-ext-v1-1-3f29da7cca76@oss.qualcomm.com
…rent block On Qualcomm SoCs where the modem (e.g. the mDSP on Shikra, VMID 43 / NAV) is the AXI master for BAM-DMUX RX transfers and the XPU enforces per-region access control, each individually DMA-mapped RX buffer requires its own XPU resource group (RG). With ~16 RGs available, the 32 per-buffer dma_map_single() calls exhaust the table and the first inbound transfer faults with an XPU violation. BAM-DMUX is a singleton (exactly one instance per SoC), so the destination VMID does not need to be a DT property; it is looked up from the compatible string's match data instead. Add struct bam_dmux_data with a single vmid field, and a shikra_data instance hardcoding QCOM_SCM_VMID_NAV for qcom,shikra-bam-dmux. When match data is present, allocate all BAM_DMUX_NUM_SKB RX buffers as a single contiguous dma_alloc_coherent() block and SCM-assign that block to HLOS plus the VMID once at probe. This reduces RG consumption from 32 to 1. The block is never reclaimed across a modem power cycle (bam_dmux_power_off() does not touch it), so the probe-time assignment covers every subsequent restart without re-assigning or reclaiming. It is reclaimed to HLOS only once, at remove or on a probe error, and if that reclaim fails it is leaked rather than returned to the page allocator. Each rx_skbs[] slot is pre-assigned its virtual and DMA address from the block, so no per-buffer mapping is needed at power-on. Because the coherent block is not page-backed, received payload is copied into a regular netdev skb before handoff to the network stack; this is an unavoidable extra copy on the XPU-enforced RX path. Platforms without match data are unaffected: rx_virt stays NULL, no coherent memory is allocated, and the per-buffer dma_map_single() path is unchanged. Co-developed-by: Deepak Kumar Singh <deepak.singh@oss.qualcomm.com> Signed-off-by: Deepak Kumar Singh <deepak.singh@oss.qualcomm.com> Signed-off-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260714-qcom-bam-dmux-vmid-ext-v1-2-3f29da7cca76@oss.qualcomm.com
…erty A SoC can have multiple BAM DMA instances. Some of these BAMs are powered by a remote processor that enforces XPU (eXternal Protection Unit) access control and reads the per-channel descriptor FIFOs as an AXI master under that remote processor's execution environment, so their FIFOs must be accessible to the remote processor's VMID; other BAM instances on the same SoC are not behind such a remote processor and must not have this property set. Add an optional qcom,vmid property listing the destination VMID(s) that the affected BAM instance's descriptor FIFOs must be accessible to. HLOS is always the source owner and must not be listed. Co-developed-by: Deepak Kumar Singh <deepak.singh@oss.qualcomm.com> Signed-off-by: Deepak Kumar Singh <deepak.singh@oss.qualcomm.com> Signed-off-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20260714-qcom-bam-dma-vmid-ext-v1-1-cef87c57b7dc@oss.qualcomm.com
…remote VMID
On Qualcomm SoCs where the BAM is powered by a remote processor that
enforces XPU access control (e.g. the mDSP on Shikra, VMID 43 / NAV),
the BAM reads the descriptor FIFO as an AXI master under the remote
execution environment. Without an SCM grant for the remote VMID, the
first descriptor enqueue faults with an XPU violation.
Parse the optional qcom,vmid DT property as a list of destination
VMIDs. When present, SCM-assign each channel's descriptor FIFO to HLOS
plus the listed VMIDs; num_vmids being non-zero is derived purely from
qcom,vmid, a board-integration property, not from the per-SoC IP data,
and is distinct from qcom,powered-remotely.
A BAM with configured VMIDs has two properties that shape the channel
lifecycle:
1. The remote firmware owns the BAM's power and reset. It may remove
power during error recovery before the driver releases its
channels, so any pipe/block register access at teardown can raise
a synchronous external abort, and a local reset is redundant as
the remote re-initialises the hardware on the next power-on.
2. TZ does not revoke the SCM grant when the remote powers down. A
FIFO assigned once stays assigned across every power cycle, and
re-assigning or reclaiming it while the remote is mid-teardown is
rejected by TZ with -EINVAL.
Handle both by keeping the descriptor FIFO as a persistent resource on
such BAMs: allocate and SCM-assign it once on the first
bam_alloc_chan(), keep it (and its grant) across power cycles, and
reclaim it to HLOS and free it only once in bam_dma_remove(). If the
final reclaim fails the remote still has access, so the buffer is
leaked rather than returned to the page allocator; the source-VMID
bitmask stored by qcom_scm_assign_mem() drives that reclaim.
bam_free_chan() on such a BAM therefore only drops local channel state
(clear ->initialized, decrement active_channels) with no MMIO and no
SCM call, so the block and pipe are re-initialised on the next
power-on while power is present. The bam_chan_init_hw() pipe reset in
bam_dma_terminate_all() is likewise skipped. reclaiming the FIFO is an
SCM call, not a register access, so bam_dma_remove() stays safe.
Platforms that do not set qcom,vmid keep num_vmids 0, make no SCM
call, and leave the alloc/free and register-access paths unchanged.
Co-developed-by: Deepak Kumar Singh <deepak.singh@oss.qualcomm.com>
Signed-off-by: Deepak Kumar Singh <deepak.singh@oss.qualcomm.com>
Signed-off-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260714-qcom-bam-dma-vmid-ext-v1-2-cef87c57b7dc@oss.qualcomm.com
# Conflicts: # arch/arm64/boot/dts/qcom/Makefile
# Conflicts: # drivers/dma/qcom/bam_dma.c
# Conflicts: # arch/arm64/configs/defconfig
# Conflicts: # arch/arm64/boot/dts/qcom/Makefile
# Conflicts: # drivers/firmware/qcom/Kconfig
# Conflicts: # arch/arm64/configs/defconfig
# Conflicts: # arch/arm64/configs/defconfig # drivers/pci/controller/dwc/pcie-qcom.c # sound/soc/qcom/qdsp6/audioreach.c
🔨 Build Failure Analysis — PR #1414PR: #1414
Verdict1 unique compilation error introduced by this PR. The error occurs in both standard and RT kernel builds, blocking all compilation. 📎 Detailed analysis: Full report |
🔨 Build Failure Analysis — PR #1414PR: #1414
VerdictThe single compilation error is introduced by this PR. The error occurs in both the standard and RT kernel builds. 📎 Detailed analysis: Full report |
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🔨 Build Failure Analysis — PR #1414PR: #1414
VerdictAll 4 errors are introduced by this PR. The new file 📎 Detailed analysis: Full report |
🔨 Build Failure Analysis — PR #1414PR: #1414
VerdictAll 4 compilation errors are introduced by this PR. The new OPE driver uses an outdated v4l2_subdev API signature. 📎 Detailed analysis: Full report |
Add an image processing driver for the Qualcomm Offline Processing Engine
(OPE). OPE is a memory-to-memory ISP block that converts raw Bayer
frames to YUV, performing white balance, demosaic, chroma enhancement,
color correction and downscaling.
The hardware architecture consists of Fetch Engines and Write Engines,
connected through intermediate pipeline modules for pix processing.
The driver exposes three video nodes per pipeline instance:
- ope_input: Bayer RAW input (V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
- ope_disp_output: YUV output (V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
- ope_params: ISP parameters (V4L2_BUF_TYPE_META_OUTPUT)
Hardware features:
- Stripe-based processing (up to 336 pixels wide per stripe)
- White balance (CLC_WB)
- Demosaic / Bayer-to-RGB (CLC_DEMO)
- Color correction matrix (CLC_CC)
- Gamma LUT (CLC_GAMMA)
- RGB-to-YUV conversion (CLC_CHROMA_ENHAN)
- MN downscaler for chroma and luma planes
Default configuration values are based on public standards such as BT.601.
Processing Model:
OPE processes frames in stripes of up to 336 pixels. Therefore, frames
must be split into stripes for processing. Each stripe is configured after
the previous one has been acquired (double buffered registers). To minimize
inter-stripe latency, stripe configurations are generated ahead of time.
The driver is split into three source files under the ope/ directory:
- core.c: the OPE m2m driver itself: probe, power management, V4L2/media
device setup, format handling, stripe generation and hardware
programming.
- pipeline.c/.h: a small declarative media-controller topology builder.
Drivers describe their entire media graph, entities (video devices,
subdevs, or base entities), their pads, and the links between them, in
a static descriptor table. The builder validates the table, allocates
and registers all entities, and creates all MC pad links. It is kept
generic but currently only used by OPE.
- params.c/.h: V4L2 ISP parameter buffer validation and dispatch. It
wraps the extensible V4L2 ISP parameters buffer format, validating
the buffer size and each per-block header before forwarding every
block to its driver-supplied handler.
A userspace libcamera support can be found at:
https://github.com/jwrdegoede/libcamera/commits/camss_pipeline_v2.2/
A test tool, camss-isp-m2m, can be found at:
https://github.com/loicpoulain/camss-isp-m2m-test
Link: https://lore.kernel.org/all/20261102-camss-isp-ope-v12-6-702254689feb@oss.qualcomm.com/
Assisted-by: LLM
Co-developed-by: Hans de Goede <johannes.goede@oss.qualcomm.com>
Signed-off-by: Hans de Goede <johannes.goede@oss.qualcomm.com>
Link: https://github.com/jwrdegoede/libcamera/commits/camss_pipeline_v2.1/
Link: https://github.com/loicpoulain/camss-isp-m2m-test
Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
Co-developed-by: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>
Signed-off-by: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>
Adding merge log file and topic_SHA1 file Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>
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Test Matrix
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LAVA Failed Case Triage SummaryPR: #1414 Job 268529 | SoC qcs6490-rb3gen2LAVA job: https://lava-oss.qualcomm.com/scheduler/job/268529 Failed test cases in LAVA job 268529 (SoC: qcs6490-rb3gen2).
Job 268530 | SoC sm8750-mtpLAVA job: https://lava-oss.qualcomm.com/scheduler/job/268530 Failed test cases in LAVA job 268530 (SoC: sm8750-mtp).
Job 268531 | SoC lemans-evkLAVA job: https://lava-oss.qualcomm.com/scheduler/job/268531 Failed test cases in LAVA job 268531 (SoC: lemans-evk).
Job 268532 | SoC qcs9100-rideLAVA job: https://lava-oss.qualcomm.com/scheduler/job/268532 Failed test cases in LAVA job 268532 (SoC: qcs9100-ride).
Job 268533 | SoC purwa-evkLAVA job: https://lava-oss.qualcomm.com/scheduler/job/268533 Failed test cases in LAVA job 268533 (SoC: purwa-evk).
Job 268534 | SoC glymur-qli-crdLAVA job: https://lava-oss.qualcomm.com/scheduler/job/268534 Failed test cases in LAVA job 268534 (SoC: glymur-qli-crd).
Job 268535 | SoC shikra-iqs-evkLAVA job: https://lava-oss.qualcomm.com/scheduler/job/268535 Failed test cases in LAVA job 268535 (SoC: shikra-iqs-evk).
Job 268537 | SoC qcs615-rideLAVA job: https://lava-oss.qualcomm.com/scheduler/job/268537 Failed test cases in LAVA job 268537 (SoC: qcs615-ride).
Job 268538 | SoC monaco-evkLAVA job: https://lava-oss.qualcomm.com/scheduler/job/268538 Failed test cases in LAVA job 268538 (SoC: monaco-evk).
Job 268539 | SoC kaanapali-mtpLAVA job: https://lava-oss.qualcomm.com/scheduler/job/268539 Failed test cases in LAVA job 268539 (SoC: kaanapali-mtp).
Job 268540 | SoC qcs8300-rideLAVA job: https://lava-oss.qualcomm.com/scheduler/job/268540 Failed test cases in LAVA job 268540 (SoC: qcs8300-ride).
Job 268541 | SoC hamoa-evkLAVA job: https://lava-oss.qualcomm.com/scheduler/job/268541 Failed test cases in LAVA job 268541 (SoC: hamoa-evk).
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Test Matrix
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Test Matrix
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Test Matrix
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Name SHA Commits
tech/bsp/clk 443bd58 9
tech/bsp/devfreq 7acfd26 8
tech/bsp/ec c46f06d 2
tech/bsp/interconnect 81fc6e2 1
tech/bsp/sched 40b3c1f 2
tech/security/firmware-smc 503110b 11
tech/bsp/soc-infra 76d8086 33
tech/bus/pci/all 29bb333 38
tech/bus/usb/all dd0f225 51
tech/debug/hwtracing f7bba91 20
tech/pmic/all d517c3e 23
tech/mem/all 5d786d3 8
tech/mm/audio/all f084244 41
tech/mm/camss b64ca4b 33
tech/mm/drm 5681492 91
tech/mm/fastrpc e808ccd 9
tech/mm/video 1e05914 45
tech/net/ath 76d931c 9
tech/net/eth 4d55657 18
tech/net/bluetooth 1ec6c24 11
tech/pm/power 29c839e 13
tech/pm/thermal 000ea55 4
tech/security/crypto 973a381 27
tech/security/optee-next 6c04332 2
tech/storage/all 5929ee0 7
tech/all/dt/qcs6490 04fd975 20
tech/all/dt/qcs9100 d0291c6 20
tech/all/dt/qcs8300 b132d5e 26
tech/all/dt/qcs615 dbe132c 16
tech/all/dt/eliza 8b9d593 9
tech/all/dt/hamoa 41f3035 29
tech/all/dt/glymur dbd0f70 31
tech/all/dt/kaanapali 328e630 19
tech/all/dt/pakala b19aeb8 10
tech/all/hawi f7bc734 16
tech/all/maili a636cc5 17
tech/all/shikra 60c8bf4 71
tech/all/config 5d707d0 91
tech/overlay/dt 7f71952 102
tech/all/workaround 8d89b91 7
tech/noup/debug/all 42fa88a 38
tech/hwe/unoq 9b67cf2 3
early/hwe/nord fcf1215 89