Pinned Loading

1. tg-full-adder-cmos tg-full-adder-cmos Public

   "1-bit full adder using transmission gate logic — Cadence Virtuoso, GPDK 0.18µm, 14.3% transistor reduction vs standard CMOS

   1

2. fpga-hardware-puf fpga-hardware-puf Public

   FPGA-based Hardware PUF implementation on Shrike FPGA using Verilog, SPN architecture, UART & SHA-256 for secure device authentication.

   Tcl 1

3. PCB_Design PCB_Design Public

   Hardware design submissions: 3S Li-ion charger, PCB design, and Arduino control system

   1

4. CanSat-ISL CanSat-ISL Public

   2-layer PCB Avionics design for CanSat mission with STM32, IMU, GPS, Altimeter & OpenRocket simulation

   1

5. riscv-rtl-to-gds riscv-rtl-to-gds Public

   Synthesizable 32-bit RISC-V (RV32I) single-cycle processor built from scratch in Verilog, timing-closed at 50 MHz, and taped out to GDSII on SkyWater 130nm using OpenLane 2.

   Verilog