GitHub - mzd95/Vending-Machine: Final project of S16 ECE156A of UCSB. Implemented in Verilog HDL with randomized test module. · GitHub

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Vending-Machine

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Final project of S16 ECE156A of UCSB. Implemented in Verilog HDL with randomized test module.

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Name		Name	Last commit message	Last commit date
HW06.cr.mti		HW06.cr.mti
HW06.mpf		HW06.mpf
VendMachine_B.v		VendMachine_B.v
VendMachine_tb.v		VendMachine_tb.v
VendMachines_tb.v		VendMachines_tb.v
VendMachines_tb.v.bak		VendMachines_tb.v.bak
auto_verification.txt		auto_verification.txt
class.v		class.v
coin_sensor_B.v		coin_sensor_B.v
dff_tb		dff_tb
dffs_tb.v		dffs_tb.v
dffs_tb.v.bak		dffs_tb.v.bak
piggyBank_B.v		piggyBank_B.v
purchaseManager_B.v		purchaseManager_B.v
report.txt		report.txt
seg_decoder_B.v		seg_decoder_B.v
self_verification.txt		self_verification.txt
sevenSegDispMngr_B.v		sevenSegDispMngr_B.v
transcript		transcript
vsim.wlf		vsim.wlf

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Final project of S16 ECE156A of UCSB. Implemented in Verilog HDL with randomized test module.

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