Edge-MPSoC: A RISC-V System-on-Chip (SoC) framework for Edge AI including RTL modules, UVM verification, firmware compilation toolchain, register map generation, and open-source simulation infrastructure.

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Directory Overview

• app/: Contains application source files (start.s) and the linker script (sections.lds). These are compiled into executable binaries for SRAM.
• include/: Contains global SystemVerilog header files (e.g., typedef.svh).
• modules/: Contains RTL designs (CPU, interconnects, wrappers, generated registers) and memory models (SRAM).

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Prerequisites & Setup

Ensure the following tools and toolchains are installed on your system:

• Verilator – Verilog/SystemVerilog simulator (v5.020, v5.026, and v5.052 have been confirmed to work with this repo)
• Surfer – Waveform viewer
• PeakRDL – SystemRDL toolchain for register generation
• RISC-V GCC Toolchain – Cross-compiler toolchain for RISC-V target architectures
• liblz4 Install with sudo apt-get install liblz4-dev

Ensure all required dependencies exist and that common_cells is located inside axi:

1. Clone Edge-MPSoC.
2. Clone the axi platform repository, commit 808e7b3.
3. Update PULP_AXI_PATH in run_soc_tb.sh to reflect the location of axi/.
4. Clone the common_cells repository inside axi/, commit 177f07a.
5. Update the location of data and exec SRAM init files (.Initfile) in modules/soc_top/soc.sv (firmware compilation steps are below) and for the data ram init file run gen_mem.sh 1024 in modules/sram_node.

For convenience, structure your directories as follows:

Edge-MPSoC/
axi/
└── common_cells/

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Register Map Generation (PeakRDL)

Use PeakRDL to generate register documentation and AXI4-Lite regblock RTL from SystemRDL specifications:

# Generate HTML documentation
peakrdl html data_sampler_wrapper_regs.rdl -o ./docs/register_map/

# Generate AXI4-Lite register block RTL
peakrdl regblock data_sampler_wrapper_regs.rdl -o generated/ --cpuif axi4-lite-flat

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Firmware Compilation

1. Assemble & Link ELF

Compile start.s into a RISC-V ELF binary using sections.lds:

• With Standard Libraries:

  riscv64-unknown-elf-gcc -march=rv32i -mabi=ilp32 -ffreestanding -nostartfiles -T sections.lds start.s -o firmware.elf

• Without Standard Libraries:

  riscv64-unknown-elf-gcc -march=rv32i -mabi=ilp32 -ffreestanding -nostartfiles -nostdlib -T sections.lds start.s -o firmware.elf

• Or Compile C file directly to hex:

  riscv64-unknown-elf-gcc -march=rv32i -mabi=ilp32 -ffreestanding -nostdlib -Wl,-T,sections.lds start.s main.c -o firmware.elf

2. Convert to Verilog Hex

Convert the ELF binary into Verilog Hex format for $readmemh memory initialization:

riscv64-unknown-elf-objcopy -O verilog --verilog-data-width=8 firmware.elf firmware.hex

3. Disassemble & Inspect ELF

Inspect disassembly and machine code contents:

riscv64-unknown-elf-objdump -d firmware.elf

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Running Simulation

Execute the SoC testbench runner script:

# Run simulation (without waveform output)
./run_soc_tb.sh

# Run simulation with waveforms (launches Surfer viewer)
./run_soc_tb.sh wf

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TODOs:

• picorv32 integration test
• axi_spi_slave integration test
• improve UVM flow
• cpu (picorv32) bootup test with sanity checks
• improve c-to-hex flow
• set up nightly regression
• FPGA prototyping
• UART integration and printing output of UART pin in Verilator simulation to a terminal in real time