[xiezyang]

Title: LATX, fix: Release dead operand and memory address temps

Summary

Release the TEST source temporaries after flag calculation and the AND result have been emitted, before translating the paired conditional instruction. This reduces temporary-register pressure when TEST and CMOVcc both access memory and prevents the itemp exhaustion reported in #524 with LATX_MT=1/2 on 16KB-page hosts. Preserve the AND result and the same-register TEST path.

Release temporary addresses after scalar floating-point, XMM and YMM memory accesses, and after copying an internally allocated address to a specified LEA destination. Reuse the existing integer-memory release condition through ra_free_mem_temp(), preserving mapped guest registers and registers reserved for the immediate cache.

Add a self-checking static x86_64 TEST+CMOVcc fixture for LATX_MT=0/1/2 and register it in latx-integration. The register allocator and page-check fallback behavior are unchanged.

Fixes #524

Validation

Validated signed head 8e191ae on a LoongArch64 host with 16KB pages, based on freshly fetched upstream master 48a9c55. Both commits contain DCO sign-offs. Their source trees are identical to the previously reviewed commits; only sign-off trailers and commit metadata changed. The fast suite and the two focused integration tests below were rerun after the rewrite. Other results were obtained earlier from the identical source tree.

• ninja -C build64 and ninja -C build32: passed; the existing build trees were up to date. This was an incremental verification, not a fresh configure/build.
• python3 lat/meson/meson.py test -C build64 --suite lat-pr-fast --print-errorlogs: 49/49 passed.
• python3 lat/meson/meson.py test -C build64 --suite latx-integration test-latx-mt-test-cmov-mem test-xcomis-patterns --print-errorlogs: 2/2 passed.
• The same registered TEST+CMOVcc regression fails against the baseline with itemp register exhausted, status=0x7f and passes against the candidate. An independent minimal guest was also run three times per mode: baseline LATX_MT=1/2 consistently received SIGABRT; candidate LATX_MT=0/1/2 always exited with status 0.
• rip-relative-cache.asm passed with LATX_IMM_REG=0000 and 1111 when run directly through test-avx-regressions.py with LATX_AVX_PREBUILT unset. These runs include JIT, cold AOT and hot AOT; the runner verifies cache loading for hot AOT.

The two corresponding Meson cache-test entries failed before guest execution because they set LATX_AVX_PREBUILT to an empty string, which the unchanged runner interprets as a prebuilt-fixture directory. Direct equivalent commands passed:

env -u LATX_AVX_PREBUILT LATX_IMM_REG=0000 python3 lat/tests/integration/test-avx-regressions.py build64/latx-x86_64 lat/tests/integration/rip-relative-cache.asm
env -u LATX_AVX_PREBUILT LATX_IMM_REG=1111 python3 lat/tests/integration/test-avx-regressions.py build64/latx-x86_64 lat/tests/integration/rip-relative-cache.asm

test-latx-16k-page-permission-i386 was skipped because clang was unavailable. No i386 runtime result, original Wine/Notepad++ workload result for this candidate, or performance benchmark is claimed. The address-release changes have no dedicated register-exhaustion RED/GREEN test.

Commands above are relative to the parent of the lat checkout, which contains build64 and build32.

Checklist

• I have read CONTRIBUTING.md.
• Every commit contains a DCO sign-off (git commit -s).
• I have included relevant build or test results, or explained why they are not applicable.