Campaign: unified coprocessor backend (Axiom.jl pattern) + roll out to repos needing acceleration

[hyperpolymath]

Goal

A single unified, optimised coprocessor backend that neatly backends the suitable kernels rather than carrying each coprocessor separately — benchmark-driven dispatch to the fastest available backend, with safe fallback.

State (from audit)

• Axiom.jl does not yet exist in the reachable tree. The working exemplar of the pattern is burble's SmartBackend (burble/server/lib/burble/coprocessor/{smart_backend,backend,zig_backend,snif_backend,elixir_backend}.ex): per-operation dispatch to the fastest backend with a published benchmark table and SNIF crash-isolation.
• Action: create the canonical Axiom.jl (Julia) as the optimised backend, generalising burble's pattern into kernel-domain dispatch.

Coprocessor elements — please confirm the canonical set

Your list was given as "10" but enumerates 11: QPU, NPU, GPU, AudioPU, I/OPU, TPU, VectorPU, ASIC-interface (extensibility slot, by-design under-specified), Physics, Maths, Cryptographic.
Candidates possibly missing (for your call): FPGA/reconfigurable (≠ fixed-function ASIC), Neuromorphic/spiking (≠ NPU), DPU/SmartNIC (unless I/OPU subsumes it), Entropy/RNG unit (natural pairing with QPU + Cryptographic). → decide the final canonical list before implementation.

Repos needing coprocessor support (from audit)

Repo	Need	Priority
affinescript	WASM codegen has no audio/GPU/NPU/math backends (BACKEND-ANALYSIS.md)	HIGH
verisimdb	tensor (verisim-tensor), HNSW vector search, semantic proofs → GPU/vector dispatch (also has the raw NIF above)	MEDIUM
developer-ecosystem/iser-tools/futharkiser	GPU manifest already exists (OpenCL/CUDA/multicore) → unify with the SmartBackend pattern	MEDIUM
burble	reference implementation — done	—

Wire-up

Expose a coprocessor-dispatch verb in the unified-zig-api so dispatch crosses the Idris2-ABI / pure-Zig-FFI seam (consistent with the no-C/no-.h + Idris2-ABI standards).

Scope

Master campaign; reachable repos = the 6; ~290 estate-wide. Per-repo sub-issues to follow.

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Filed via Claude Code — https://claude.ai/code/session_01JNCDaWMB8NV6nAPrvmTg4w

[hyperpolymath]

RULING D145 (2026-09-30T14:13Z) · scope: repo · basis: owner (direct answer, selector)

OWNER TEXT: "is it togglable - ideally all would gain the integration, but if [not], then your recommendation" — every element (incl. FPGA/DPU/RNG) is a togglable entry; target = all elements gain a kernel backend; an element without a backend is listed but toggled OFF until it has one (resolves 10-vs-11)

surface: hyperpolymath/standards#787 (comment)

The open question in this issue is answered by the ruling above; future agents should act on it rather than re-ask.