Asynchronous dual clock FIFO

Overview

This repository stores a verilog description of dual clock FIFO. A FIFO is a convenient circuit to exchange data between two clock domains. It manages the RAM addressing internally, the clock domain crossing and informs the user of the FIFO fillness with "full" and "empty" flags.

It is widely inspired by the excellent article from Clifford Cummings, Simulation and Synthesis Techniques for Asynchronous FIFO Design.

The simulation testcases available use Icarus Verilog and SVUT tool to run the tests.

The FIFO is fully functional and used in many successful projects.

Usage

RTL sources are present in RTL folder under three flavors:

• rtl/async_fifo.v: a basic asynchronous dual-clock FIFO
• rtl/async_bidir_fifo.v: two instance of the first one into a single top level for full-duplex channel
• rtl/async_bidir_ramif_fifo.v: same than previous but with external RAM

The three FIFOs have a list file to get the associated fileset.

The testbench in sim/ provides an example about the instance and the configuration.

Development

See CONTRIBUTING.md for support requests, contribution expectations, and the project-local OpenCode workflow.

To use the OpenCode flow, start a session in this repository and run the commands as needed:

1. /rtl-plan <change> to inspect the design and plan a scoped change without editing files.
2. /rtl-implement <change> to implement the agreed change and run relevant checks.
3. /rtl-verify <change> to run checks and report their exact results.
4. /rtl-review to get a read-only review of staged and unstaged changes.

Planning and implementation run in the current session. Verification and review run as child sessions; they are not automatic, so inspect their reports before proceeding. For example, use /rtl-plan Fix the full-write behavior in the bidirectional FIFO, then invoke implementation, verification, and review separately.

All three top levels have the same parameters:

• DSIZE: the size in bits of the datapath
• ASIZE: the size in bits of the internal RAM address bus. This implies the FIFO can be configured only with power of 2 depth

The internal-memory FIFO variants use first-word-fall-through reads: rdata shows the current head word and is valid when empty is deasserted. The external-RAM wrapper's read timing is determined by the attached RAM.

License

Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. imitations under the License.