Skip to content

Measure ellipsoid ode45 output-grid effect before source refinement - #659

Closed
cmccomb wants to merge 4 commits into
masterfrom
codex/ellipsoid-output-ab-599
Closed

cmccomb wants to merge 4 commits into
masterfrom
codex/ellipsoid-output-ab-599

Conversation

@cmccomb

@cmccomb cmccomb commented Oct 24, 2026 •

Copy link
Copy Markdown
Member

Purpose

Issue #599's pinned R2025b Nonlinear_Hydro/ode45 source screen lost three hosted runners while simulating the all-clock 0.000625 s arm, before any scientific gate completed. This diagnostic checks whether coarser output logging can reduce stored source histories without materially changing the trajectory. It is based on the remote head of draft PR #655 and touches only cmudrc/wec-sim-python.

Controlled comparison

For both Regular and RegularCIC, two copied application inputs retain simu.dt, Simulink MaxStep, nonlinearDt, and cicDt at 0.00125 s. One leaves dtOut=0.00125 s; the other explicitly sets only dtOut=0.005 s. The pinned simulation class may also derive Paraview output timing from dtOut; all physical clocks remain fixed. The source is pinned to WEC-Sim core 0753b2e47f2457c078751dcfe5d251d1767b80ab and Applications d53d4d4c9eda2581f04204f5d394a6ef84bb099e under R2025b.

The test predeclares common-grid A/B limits of 10 µm heave and PTO stroke, 20 µm/s heave and PTO speed, 30 N PTO force, and 30 W absorbed power. Full-grid versus sampled-grid signed work must differ by under 0.001%; sampled full-output versus coarse-output signed work must differ by under 0.01%. Wave and time arrays have stricter identity checks. Restoring/excitation/acceleration differences are logged as diagnostics.

Measured result

At exact head 472996b0cc628816a4959506fe11efaaa7a9d5c2, run 40104326372 passed both matrix cases. Every common-grid heave, speed, PTO stroke, PTO speed, PTO force, and absorbed-power difference was exactly zero; wave and time identities passed. Restoring, excitation, and acceleration diagnostic differences were also zero.

Case Full 1.25 ms signed work Full arm sampled at 5 ms 5 ms output arm
Regular 20,069,978.377 J 20,069,980.819 J 20,069,980.819 J
RegularCIC 20,097,460.025 J 20,097,457.853 J 20,097,457.853 J

The full-to-sampled relative work differences were 1.2166e-7 and 1.0807e-7; sampled-to-output-only work differences were exactly zero. This establishes output-clock neutrality at the tested 1.25 ms physical step only. It does not establish neutrality at the planned 0.625 ms physical step. The original published 0.05 s gate and PR #655's derived four-step physical limits stay unchanged; no badge or reference-status promotion follows from this A/B alone.

cmccomb commented Oct 24, 2026

Copy link
Copy Markdown
Member Author

The controlled 0.00125 s output-grid A/B check and its fresh workflow were consolidated into merged #655. Its evidence is preserved there, including the exact common-grid result. This diagnostic PR is superseded.

@cmccomb cmccomb closed this Oct 24, 2026
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

1 participant