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video: analog H-size (CRT width stretch) via 54 MHz retimer #6

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video: analog H-size (CRT width stretch) via 54 MHz retimer #6

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4a7c2d6
video: migrate the video master clock to 54 MHz
asturur Sep 28, 2026
e744c03
video: harden the H-size retimer and register its testbenches
asturur Sep 28, 2026
00db1c7
video: decode the interim word2 H-size control beat
asturur Sep 28, 2026
702c0a4
video: map the saved H size onto the retimer controls
asturur Sep 28, 2026
f9093fc
video: wire the H-size retimer into the analog output path
asturur Sep 28, 2026
e9310d2
tb: split the reader testbench to fit CI's per-test wall clock
asturur Sep 28, 2026
bb4dba3
osd: pin the analog OSD dot width at the 54 MHz video clock
asturur Sep 28, 2026
1058a8d
video: sample the H-size retimer at the 13.5 MHz OSD dot rate
asturur Sep 29, 2026
df9dc75
video: vertical shrink via extra blank lines (word2 v_size)
asturur Oct 1, 2026
1401575
Revert "video: vertical shrink via extra blank lines (word2 v_size)"
asturur Oct 2, 2026
3f08fe7
docs: word2 ownership now shared with the frontend
asturur Oct 2, 2026
3a3535e
Merge branch 'master' into crt-hsize
asturur Oct 12, 2026
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34 changes: 18 additions & 16 deletions files.qip
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Original file line number Diff line number Diff line change
@@ -1,16 +1,18 @@
set_global_assignment -name QIP_FILE rtl/pll_video.qip
set_global_assignment -name SDC_FILE menu.sdc
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name VERILOG_FILE rtl/lfsr.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/cos.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/native_video_reader.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/native_video_timing.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/native_video_top.sv
set_global_assignment -name SYSTEMVERILOG_FILE menu.sv
set_global_assignment -name SYSTEMVERILOG_FILE sys/mister_magik_vblank_latch.sv
set_global_assignment -name SYSTEMVERILOG_FILE sys/mister_magik_latch_sys_top_bridge.sv
set_global_assignment -name SYSTEMVERILOG_FILE sys/mister_magik_bootstrap_black.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/zaparoo_bootstrap_video.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/zaparoo_snow_phase.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/zaparoo_pixel_enable.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/zaparoo_snow_enable.sv
set_global_assignment -name QIP_FILE rtl/pll_video54.qip
set_global_assignment -name SDC_FILE menu.sdc
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name VERILOG_FILE rtl/lfsr.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/cos.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/native_video_reader.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/native_video_timing.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/native_video_top.sv
set_global_assignment -name SYSTEMVERILOG_FILE menu.sv
set_global_assignment -name SYSTEMVERILOG_FILE sys/mister_magik_vblank_latch.sv
set_global_assignment -name SYSTEMVERILOG_FILE sys/mister_magik_latch_sys_top_bridge.sv
set_global_assignment -name SYSTEMVERILOG_FILE sys/mister_magik_bootstrap_black.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/zaparoo_bootstrap_video.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/zaparoo_snow_phase.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/zaparoo_pixel_enable.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/zaparoo_snow_enable.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/zaparoo_hretime.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/zaparoo_hsize_map.sv
6 changes: 3 additions & 3 deletions menu.sdc
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Original file line number Diff line number Diff line change
@@ -1,12 +1,12 @@
# Core-level timing constraints (processed after sys/sys_top.sdc).

# CLK_VIDEO comes from a dedicated PLL (rtl/pll_video.v) and is asynchronous
# CLK_VIDEO comes from a dedicated PLL (rtl/pll_video54.v) and is asynchronous
# to every other clock in the design: all crossings into and out of the video
# domain go through two-flop synchronizers or the line FIFO's dual-clock
# logic (rtl/native_video_reader.sv, rtl/native_video_top.sv). Without this
# group, derive_pll_clocks leaves the 27 MHz output related to the other
# group, derive_pll_clocks leaves the 54 MHz output related to the other
# clocks (shared 50 MHz reference, and absent from sys_top.sdc's exclusive
# groups), and the fitter tries to close those CDC paths against a ~1 ns
# edge relationship.
set_clock_groups -asynchronous \
-group [get_clocks { *|pll_video|pll_video_inst|altera_pll_i|*[*].*|divclk}]
-group [get_clocks { *|pll_video54|pll_video54_inst|altera_pll_i|*[*].*|divclk}]
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