[lkdvos]

Closes #578.

This unifies the CPU and GPU tree transformers into a single data structure per fusion style, while keeping the kernel implementations themselves separate.

Design

Both transformers are structs of arrays of isbits elements, such that the host version is moved to the GPU with Adapt.adapt. This replaces DeviceUniqueTreeTransformer and DeviceGenericTreeTransformer.

• UniqueTreeTransformer: coeffs, structs_dst, structs_src and n + 1 work_offsets. The transformation is a bijection between the fusion trees, so the entries are stored in the canonical order of the destination.
• GenericTreeTransformer: reuses a UniqueTreeTransformer for the single-tree blocks, and stores the multi-tree blocks as concatenated (square) recoupling matrices and locators, described by tree_offsets, coeff_offsets and work_offsets.

The type of the locators depends on the SubblockLayout of either tensor, which is now part of the transformer cache key:

• StridedLayout (TensorMap): (sizes, strides, offset) for the destination and (strides, offset) for the source, with the source strides permuted by p in advance. For unique transformers, the destination structure is shared with the space.
• PositionalLayout (any other AbstractTensorMap, e.g. DiagonalTensorMap): subblock positions into subblocks(t), and p is applied in the kernel.

The CPU kernels now operate on the flat data vector of a TensorMap instead of StridedSubblocks, which is removed. For the generic transformer, the permutation is now applied when packing the source blocks, such that the unpacking is a trivial strided addition.

Benchmarks

Single-threaded permute!, main vs this branch, on an exclusive AMD EPYC 7742 (rome) node:

• Unique (U1, Z2, U1×U1, fermion parity): 0.84–1.02×, where tensors with large subblocks gain 7–16%. This comes from visiting the blocks in the order of the destination (sequential writes), as confirmed by a separate diagnostic that compares both block orders on the same transformer data.
• Generic (SU2, A4, fermion parity×SU2×U1): 0.91–1.04×.
• Pre-permuting the source strides has no measurable effect.
• Small-block cases (e.g. U1 with 231 subblocks of 16 elements) show ±10% differences that are stable within a job but switch between Float64 and ComplexF64 across nodes, and are entirely inside the kernel, which performs identical per-block work on both revisions. This is attributed to code layout rather than to the changes here.

The multi-threaded behaviour (32 threads) is still under investigation: there, the results vary between 0.66× and 1.65× for tensors with many small subblocks, where main also slows down with more threads.

Testing

• Full (non---fast) CPU test files for index manipulations, diagonal tensors, braiding tensors, planar operations, contractions and construction, plus cuda/tensors and cuda/planar on an RTX A6000.
• Additional checks for all combinations of strided and positional layouts on multi-tree blocks, with and without conjsrc.

🤖 Generated with Claude Code