- 🔭 I’m currently working on fuzzing using the ARM CoreSight tracing component.
- 🌱 I’m interested in software/hardware security solutions and looking to learn more about their OS integration!
- ⚡ I worked on the RISC-V ISA, extending it for the security of language VMs (such as Pharo)
- 🧑🎓 I recently defended my thesis intitled "Hardware Security for Just-in-Time Compilation in Language Virtual Machines", you can download the slides here (in French) or the complete thesis manuscript here (in English).
- 📫 How to reach me: quentin.ducasse@centralesupelec.fr
🐙
Working on Hardware-Software Security co-design
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CentraleSupelec
- Rennes
- qducasse.github.io
- @quentin-ducasse.bsky.social
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pharo-vm-riscv
pharo-vm-riscv PublicForked from pharo-project/pharo-vm
This is the VM used by Pharo
Smalltalk 1
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fdia_simulation
fdia_simulation Public archive🛫 Air traffic controller simulator using simulated planes/radars. Objective - impact of a compromised radar and FDI attack on state estimators
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brevibench
brevibench Public archive🧠 Benchmark facility to train networks on different datasets for PyTorch/Brevitas
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cva6
cva6 PublicForked from openhwfoundation/cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Assembly 2
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