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* Memory interfaces registration was supported * Minor formatting
* :writeMem, :readMem statements were preserved for native simulator gen (backward compatibility) * Memory Interfaces (function names) were set as statement attributes
* TODO:
* move cpu_state.rb into common part of the sim gen scripting
* Memory Access implementations were temporarily
placed into arch specific sim library cpu_state_ext.cc
* Sim Lira/Native targets were set up
* TODO: Sepearate directories serialization & codegen as follows:
-- Protea/
-- simgen/
-- generic/
-- native/
-- lira/
-- ir/
-- native/
-- lira/
* In addition to the previous map section, we propose ordered operand list with specific map sections per-operand
* Removed string-driven programming in operand definition * Operands was applied in "RISC-V/encoding.rb" description
- fetch LIRA as third-party dependency via CPM (release v0.1.1) - drop vendored lib/lira; resolve lira/ requires via RUBYLIB - fix encode snippet generation: shift fields by their low bit position (was MSB), emit correct const widths - give getPC/setPC environment functions the 'pc' attribute - add fence.i instruction to RV32I - move pc into a dedicated 'Program Counter' register file - relax Ruby/Python version requirements (>= semantics)
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