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[Draft] Lira stable v0.1.1
- #25
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[Draft] Lira stable v0.1.1
#25
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Commits on Jun 7, 2026
Add Simtests: snippetbased and C.
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Add tests in workflow.
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Add interface functions. Small codegen fix.
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Add target dependent file to implement interface functions. Add LLVM based clang-format.
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Remove redundant whitespaces. Add status message.
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Added --propagate-exit flag.
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Start to use CTest instead of python-scripts. Add test presets in CMakePresets.
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Add new presets.
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Describe RV32M
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Decoder fix
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Small fixes.
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Removed on push in workflow.
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Add small improvements
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Remove xlen field. Small cmake improvement
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fix
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fix
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Add some tests for sim
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Clang-format
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Add ctests to run by cached-interp sim
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Update
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Fix div by zero handling
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Fix div by zero handling
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Add more snippet tests
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[lib] Memory ifaces dynamic registry supported
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Commits on Jun 8, 2026
[lib] Introduced LIRA Ruby Lib
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[lib] LIRA Seriazalization Support
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[lib] Decode Snippets serialization caching
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Commits on Jun 9, 2026
[ser] Serialization updated
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[sim-gen] Introduced LIRA-Driven Sim Gen
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[sim-lib] Temporary Stack access update
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[IR] Added LIRA IR temporary
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Commits on Jun 11, 2026
[simgen] Debug PC print
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[simgen] Instructions w/ empty body supported
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[ser] Sign extension fix
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[sim-gen] PC debug print removed
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[RV32I] Shift (I type) instructions enc upd
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Commits on Jun 12, 2026
[simlib] Stack Pointer set updated
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[ser] LIRA IR serialization shift fix
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[simgen] Removed redundant getter
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[simgen] Base Ops codegen was synced w/ LIRA Ops
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Commits on Jun 13, 2026
[ser] Binary Ops serialization refactoring
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[IR] LIRA IR updated
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Commits on Jun 15, 2026
[ADL, ser] Memory Interface names weere committed on ADL side
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[simgen] CPU State codegen was unified
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[simgen] CPP types gen refactored
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[simgen] Lira Exec Engine & Interpreted codegen refactored
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[infra] Sim gen targets were configured
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LIRA IR updated
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[ser] Major LIRA serizalier refactoring
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[simgen] Cpp Codegen major refactoring
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Commits on Jun 16, 2026
[lib, sim_gen] Operations register & look up was supported
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[lira] Operations added
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[ser] Encode & Decode constraints were supported
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[simgen] Decode constraints were supported in decoder gen
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[ADL] Introduced Operands List & Mapping
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[ser] Operand List & Map sections serialization supported
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[simgen] Decode & Constraint snipptets refactoring
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LIRA IR updated
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[ser, simgen] Base Ops caching added into lookup instead of deserialization
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Introduced base operations enum instead of strings
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Refactored
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Aliases support
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[simgen] Redundant arch hash was removed
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[infra, simgen] cpu_state.cc removed from the build
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[simgen] Read Reg statement in decoder is prohibited
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[ADL, simgen] Single :map section is deprecated
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[ser] Added Field resolve function
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[simgen] Introduced decode tree
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Commits on Jun 17, 2026
[ADL, Target] Introduced Operand & OperandBuilder
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[infra] Build upd
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LIRA IR updated
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Commits on Jun 24, 2026
[lira] LIRA Library updated
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[IR] LIRA IR removed
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[simgen] Simgen sync w/ LIRA lib update
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Commits on Oct 21, 2026
Use LIRA v0.1.1 via CPM instead of vendored copy
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Remove sim_gen_lira: redundant LIRA-based sim generator (replaced by lira-simgen-lib)
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Remove LIRA serialization from Protea: converter moves to lira-simgen-lib
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