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[RISCV, SimGen] Add rv32m description. Fix decoder generator. - #17

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uslsteen merged 15 commits into
ProteusLab:masterfrom
egorshamshura:rv32m
Oct 27, 2026
Merged

uslsteen merged 15 commits into
ProteusLab:masterfrom
egorshamshura:rv32m

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@uslsteen uslsteen self-assigned this Oct 23, 2026
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uslsteen requested review from derzhavin3016 and removed request for derzhavin3016 October 23, 2026 13:06

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Apologies for the slow review.
This pull request spent a long time in Egor Shamshura’s repo fork.
I have updated it with recent commits from the fork repository’s master branch and am ready to merge it.

@uslsteen
uslsteen removed the request for review from derzhavin3016 October 27, 2026 11:19
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uslsteen merged commit 4fa09bc into ProteusLab:master Oct 27, 2026
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@uslsteen uslsteen added ISA description Architecture Description Language related task simulator Simulation related task long-term labels Oct 27, 2026
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2 participants