Hardware and firmware engineer designing PCIe endpoints that the host OS treats as real silicon. The work starts at the transistor boundary: RTL written in SystemVerilog, synthesized through Vivado, flashed to Artix-7 FPGAs.
What I build:
- Full PCIe config-space emulation including capability chains, BAR decode, and AHCI register sets
- C# / .NET 8 / Avalonia desktop apps with native JTAG and kernel driver interop
- Windows storage and kernel subsystem analysis to validate firmware correctness
- SystemVerilog AHCI and ATA engines with DMA descriptor rings
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FPGA board management application built with Avalonia UI on .NET 8. Detects FPGA boards over JTAG via CH347, reads silicon DNA, and flashes firmware through an embedded OpenOCD instance. Ships as a single-file self-contained Windows binary with all drivers and tools bundled as encrypted resources.
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Fork of the open-source physical memory acquisition library with a targeted reliability fix for FPGA-based PCIe DMA hardware over FT601 USB. Eliminates intermittent device-not-found failures caused by read-pipe desync on cold opens, without touching the data path or adding re-init overhead.
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Hardware & Firmware
Software & Tooling
Releases are unsigned. SmartScreen will warn on first launch. Source is available — build from source if preferred.