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chipStar: do not use warpSize as a constant expression - #6

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chipstar-runtime-warpsize
Oct 14, 2026
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pvelesko merged 1 commit into
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chipstar-runtime-warpsize

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chipStar is making device-side warpSize a run-time value, as HIP 7 did (CHIP-SPV/chipStar#1934). warp_size(), device_warp_size() and block_radix_rank_match::warp_size are constexpr and return warpSize, so every TU including rocPRIM fails to compile against that change.

On chipStar these now use CHIP_DEFAULT_WARP_SIZE, the width chipStar pins warp-synchronous kernels to. It is defined by every chipStar version, so this builds against chipStar both before and after that PR.

This PR was generated using AI

@pvelesko
pvelesko force-pushed the chipstar-runtime-warpsize branch 2 times, most recently from 32732a0 to ef0ca04 Compare October 14, 2026 03:46
chipStar is making device-side warpSize a run-time value, as HIP 7 did
on AMD ("warpSize is no longer a constexpr", hip-7-changes.rst). This
fork's warp_size(), device_warp_size() and block_radix_rank_match's
warp_size are constexpr and return warpSize, so every TU including
rocPRIM (rocThrust, hipCUB, Kokkos with ROCTHRUST=ON) fails with
"no function template matches function template specialization
'logical_lane_id'".

On chipStar, HipWarpsPass pins every kernel that uses subgroup
operations or __shared__ memory to CHIP_DEFAULT_WARP_SIZE (32, or 8 on
Mali builds), which rocPRIM kernels always do, so that constant is the
width they run at. Upstream rocPRIM solved the same problem with
arch::wavefront::size()/min_size()/max_size(); this is the minimal
equivalent for the fork.
@pvelesko
pvelesko force-pushed the chipstar-runtime-warpsize branch from ef0ca04 to 954e39d Compare October 14, 2026 10:01
@pvelesko
pvelesko merged commit ef3c27e into main Oct 14, 2026
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