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Fix gated FlashAttention benchmark bindings - #137
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Materialize the distinct production gate buffer when generating standalone FlashAttention cases, validate its alignment and strided capacity, and cover the contract with focused generator tests. Assisted-by: Codex
Select a ten-way reduction unroll only for same-format Q8_0 gate/up weights at token count one, preserving the existing schedule for Q4 and generic low-token routes. Assisted-by: Codex
Integrate reusable Q1_0 decode-state naming and paired-row scale reuse before full model correctness and performance validation. Assisted-by: Codex
Route contiguous F32 RMSNorm multiply cases with one to four tokens and hidden widths 2048 through 5120 through a striped workgroup schedule. Preserve the existing publication, strided, add, and unsupported-shape routes as controls. Assisted-by: Codex
rsuderman
merged commit Oct 7, 2026
8108322
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AMD-Ecosystem:hrx-graph-develop-v2
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