From 535d7aa79c10a5aa3e44fd9938053ce675d2d1d1 Mon Sep 17 00:00:00 2001 From: Mohammad Rafi Shaik Date: Mon, 29 Jun 2026 19:46:33 +0530 Subject: [PATCH] FROMLIST: soundwire: qcom: Add set_channel_map support to SWR master DAI Add .set_channel_map support to the SWR master DAI so the ASoC layer can program per-port channel masks used by port_enable(). Fix several issues in channel map handling: clip programming to available ports to avoid out-of-bounds access, use 1-based port indexing, and store TX/RX masks separately. Also track per-direction validity and select the effective mask based on port role to avoid incorrect precedence and ensure full-width masks are preserved. Fall back to the SDW stream-provided channel mask when no mapping is configured preserving existing behaviour. Link: https://lore.kernel.org/all/20261105-soundwire_channel_map-v2-2-5efe2021552a@oss.qualcomm.com/ Signed-off-by: Mohammad Rafi Shaik --- drivers/soundwire/qcom.c | 54 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c index 7b1d4adc8decf..14fa3fd472770 100644 --- a/drivers/soundwire/qcom.c +++ b/drivers/soundwire/qcom.c @@ -164,6 +164,10 @@ struct qcom_swrm_port_config { u8 word_length; u8 blk_group_count; u8 lane_control; + u8 tx_ch_mask; + u8 rx_ch_mask; + bool tx_ch_map_valid; + bool rx_ch_map_valid; }; /* @@ -1161,12 +1165,28 @@ static int qcom_swrm_port_enable(struct sdw_bus *bus, { u32 reg; struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); + struct qcom_swrm_port_config *pcfg; u32 val; u32 offset = ctrl->reg_layout[SWRM_OFFSET_DP_PORT_CTRL_BANK]; reg = SWRM_DPn_PORT_CTRL_BANK(offset, enable_ch->port_num, bank); ctrl->reg_read(ctrl, reg, &val); + pcfg = &ctrl->pconfig[enable_ch->port_num]; + + mutex_lock(&ctrl->port_lock); + if (enable_ch->port_num <= ctrl->num_dout_ports) { + if (pcfg->rx_ch_map_valid) + enable_ch->ch_mask = pcfg->rx_ch_mask; + else if (pcfg->tx_ch_map_valid) + enable_ch->ch_mask = pcfg->tx_ch_mask; + } else { + if (pcfg->tx_ch_map_valid) + enable_ch->ch_mask = pcfg->tx_ch_mask; + else if (pcfg->rx_ch_map_valid) + enable_ch->ch_mask = pcfg->rx_ch_mask; + } + mutex_unlock(&ctrl->port_lock); if (enable_ch->enable) val |= (enable_ch->ch_mask << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT); @@ -1386,6 +1406,39 @@ static void *qcom_swrm_get_sdw_stream(struct snd_soc_dai *dai, int direction) return ctrl->sruntime[dai->id]; } +static int qcom_swrm_set_channel_map(struct snd_soc_dai *dai, + unsigned int tx_num, const unsigned int *tx_slot, + unsigned int rx_num, const unsigned int *rx_slot) +{ + struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); + unsigned int max_ports = ctrl->nports; + unsigned int i; + + if ((tx_num && !tx_slot) || (rx_num && !rx_slot)) + return -EINVAL; + + mutex_lock(&ctrl->port_lock); + for (i = 1; i <= max_ports; i++) { + ctrl->pconfig[i].tx_ch_map_valid = false; + ctrl->pconfig[i].rx_ch_map_valid = false; + + /* TX setup */ + if (tx_slot && i < tx_num) { + ctrl->pconfig[i].tx_ch_mask = tx_slot[i]; + ctrl->pconfig[i].tx_ch_map_valid = true; + } + + /* RX setup */ + if (rx_slot && i < rx_num) { + ctrl->pconfig[i].rx_ch_mask = rx_slot[i]; + ctrl->pconfig[i].rx_ch_map_valid = true; + } + } + mutex_unlock(&ctrl->port_lock); + + return 0; +} + static int qcom_swrm_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { @@ -1422,6 +1475,7 @@ static const struct snd_soc_dai_ops qcom_swrm_pdm_dai_ops = { .shutdown = qcom_swrm_shutdown, .set_stream = qcom_swrm_set_sdw_stream, .get_stream = qcom_swrm_get_sdw_stream, + .set_channel_map = qcom_swrm_set_channel_map, }; static const struct snd_soc_component_driver qcom_swrm_dai_component = {