Relax memory ordering of shared refcount atomics

[kddnewton]

Feature or enhancement

Proposal:

In the free-threaded build, all operations on ob_ref_shared use sequentially consistent atomics. Full ordering is stronger than the biased reference counting protocol requires, and on ARM64 the ordered instructions are measurably slower under contention. Instead, we could (and I think should) match what C++ shared_ptr implementations do which is relaxed increfs and acquire/release decrefs ^{1 2 3 4}.

Has this already been discussed elsewhere?

No response given

Links to previous discussion of this feature:

No response

Linked PRs

• gh-156132: Relax memory ordering of shared refcount atomics #156135

Footnotes

1. https://github.com/llvm/llvm-project/blob/a005951a12a9f5cd1e11e9c59cbb52d74fcffe4f/libcxx/include/__memory/shared_count.h#L27-L42 ↩

2. https://github.com/boostorg/smart_ptr/blob/6e945160d788b8efdfc49ba4af1f8797cacd7c97/include/boost/smart_ptr/detail/sp_counted_base_std_atomic.hpp#L41-L66 ↩

3. https://github.com/rust-lang/rust/blob/8925ea358a0f265ca61026aadc7ecc506c545cbe/library/alloc/src/sync.rs#L2409-L2420 ↩

4. https://github.com/rust-lang/rust/blob/8925ea358a0f265ca61026aadc7ecc506c545cbe/library/alloc/src/sync.rs#L2875-L2903 ↩

[picnixz]

Do you have an idea of how measurable the slowdown is? and how much relaxed aromics would save you?

[kddnewton]

Do you have an idea of how measurable the slowdown is? and how much relaxed aromics would save you?

Sorry I put benchmarks in the PR not the issue. It varies by ARM hardware, anywhere from 2% to 16% on the benchmarks provided.

[picnixz]

Ah I see. I am on mobile so it ks hard to read. Can you provide a summary using pyperf for a typical program/using pyperformance for a larger effect? pyperformance suite is large so if you do not have time it is ok.

I believe 16% is fair to make the change but I'll let the FT experts decide on the course. I am also quite sure it is not the only place where relaxed add is needed (we have a bunch of "custom" incref/decref when managing our own buffers though they are usually not hot paths).

[kddnewton]

@picnixz the issue I had with pyperformance is that it doesn't really exercise this code path. This code path is only going to benefit when you have multiple cross-thread increfs on the same object (since that's the only real instruction that changes here, specifically on ARM). I couldn't find a pyperformance benchmark that actually did that. But maybe I missed one?

[picnixz]

Ah if there is none, do not worry. I thought we had one for such cases (maybe those working on FT can tell you more).